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library/ad9361- add dac clk sel

main
Rejeesh Kutty 2016-08-26 10:30:46 -04:00
parent 74bc498a6d
commit 9799599eee
4 changed files with 33 additions and 8 deletions
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12
library/axi_ad9361/axi_ad9361.v
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@ -312,10 +312,11 @@ module axi_ad9361 (
// internal signals
wire adc_ddr_edgesel;
wire adc_ddr_edgesel_s;
wire adc_valid_s;
wire [47:0] adc_data_s;
wire adc_status_s;
wire dac_clksel_s;
wire dac_valid_s;
wire g_dac_valid_s;
wire [47:0] dac_data_s;
@ -413,9 +414,10 @@ module axi_ad9361 (
.adc_data (adc_data_s),
.adc_status (adc_status_s),
.adc_r1_mode (adc_r1_mode),
.adc_ddr_edgesel (adc_ddr_edgesel),
.adc_ddr_edgesel (adc_ddr_edgesel_s),
.dac_valid (g_dac_valid_s),
.dac_data (dac_data_s),
.dac_clksel (dac_clksel_s),
.dac_r1_mode (dac_r1_mode),
.tdd_enable (tdd_enable_s),
.tdd_txnrx (tdd_txnrx_s),
@ -471,9 +473,10 @@ module axi_ad9361 (
.adc_data (adc_data_s),
.adc_status (adc_status_s),
.adc_r1_mode (adc_r1_mode),
.adc_ddr_edgesel (adc_ddr_edgesel),
.adc_ddr_edgesel (adc_ddr_edgesel_s),
.dac_valid (g_dac_valid_s),
.dac_data (dac_data_s),
.dac_clksel (dac_clksel_s),
.dac_r1_mode (dac_r1_mode),
.tdd_enable (tdd_enable_s),
.tdd_txnrx (tdd_txnrx_s),
@ -572,7 +575,7 @@ module axi_ad9361 (
.adc_data (adc_data_s),
.adc_status (adc_status_s),
.adc_r1_mode (adc_r1_mode),
.adc_ddr_edgesel (adc_ddr_edgesel),
.adc_ddr_edgesel (adc_ddr_edgesel_s),
.dac_data (dac_data_s),
.up_dld (up_adc_dld_s),
.up_dwdata (up_adc_dwdata_s),
@ -616,6 +619,7 @@ module axi_ad9361 (
.dac_clk (clk),
.dac_valid (dac_valid_s),
.dac_data (dac_data_s),
.dac_clksel (dac_clksel_s),
.dac_r1_mode (dac_r1_mode),
.adc_data (adc_data_s),
.up_dld (up_dac_dld_s),

13
library/axi_ad9361/axi_ad9361_cmos_if.v
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@ -74,6 +74,7 @@ module axi_ad9361_cmos_if (
dac_valid,
dac_data,
dac_clksel,
dac_r1_mode,
// tdd interface
@ -139,6 +140,7 @@ module axi_ad9361_cmos_if (
input dac_valid;
input [47:0] dac_data;
input dac_clksel;
input dac_r1_mode;
// tdd interface
@ -211,6 +213,8 @@ module axi_ad9361_cmos_if (
reg txnrx_n_int = 'd0;
reg enable_p_int = 'd0;
reg txnrx_p_int = 'd0;
reg dac_clkdata_p = 'd0;
reg dac_clkdata_n = 'd0;
reg locked_m1 = 'd0;
reg locked = 'd0;
@ -400,6 +404,11 @@ module axi_ad9361_cmos_if (
txnrx_p_int <= txnrx_n_int;
end
always @(posedge l_clk) begin
dac_clkdata_p <= dac_clksel;
dac_clkdata_n <= ~dac_clksel;
end
// receive data interface, ibuf -> idelay -> iddr
generate
@ -500,8 +509,8 @@ module axi_ad9361_cmos_if (
.IODELAY_GROUP (IO_DELAY_GROUP))
i_tx_clk (
.tx_clk (l_clk),
.tx_data_p (1'b1),
.tx_data_n (1'b0),
.tx_data_p (dac_clkdata_p),
.tx_data_n (dac_clkdata_n),
.tx_data_out (tx_clk_out),
.up_clk (up_clk),
.up_dld (up_dac_dld[13]),

13
library/axi_ad9361/axi_ad9361_lvds_if.v
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@ -80,6 +80,7 @@ module axi_ad9361_lvds_if (
dac_valid,
dac_data,
dac_clksel,
dac_r1_mode,
// tdd interface
@ -151,6 +152,7 @@ module axi_ad9361_lvds_if (
input dac_valid;
input [47:0] dac_data;
input dac_clksel;
input dac_r1_mode;
// tdd interface
@ -227,6 +229,8 @@ module axi_ad9361_lvds_if (
reg txnrx_n_int = 'd0;
reg enable_p_int = 'd0;
reg txnrx_p_int = 'd0;
reg dac_clkdata_p = 'd0;
reg dac_clkdata_n = 'd0;
reg locked_m1 = 'd0;
reg locked = 'd0;
@ -452,6 +456,11 @@ module axi_ad9361_lvds_if (
txnrx_p_int <= txnrx_n_int;
end
always @(posedge l_clk) begin
dac_clkdata_p <= dac_clksel;
dac_clkdata_n <= ~dac_clksel;
end
// receive data interface, ibuf -> idelay -> iddr
generate
@ -554,8 +563,8 @@ module axi_ad9361_lvds_if (
.IODELAY_GROUP (IO_DELAY_GROUP))
i_tx_clk (
.tx_clk (l_clk),
.tx_data_p (1'b0),
.tx_data_n (1'b1),
.tx_data_p (dac_clkdata_p),
.tx_data_n (dac_clkdata_n),
.tx_data_out_p (tx_clk_out_p),
.tx_data_out_n (tx_clk_out_n),
.up_clk (up_clk),

3
library/axi_ad9361/axi_ad9361_tx.v
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@ -44,6 +44,7 @@ module axi_ad9361_tx (
dac_clk,
dac_valid,
dac_data,
dac_clksel,
dac_r1_mode,
adc_data,
@ -106,6 +107,7 @@ module axi_ad9361_tx (
input dac_clk;
output dac_valid;
output [47:0] dac_data;
output dac_clksel;
output dac_r1_mode;
input [47:0] adc_data;
@ -354,6 +356,7 @@ module axi_ad9361_tx (
.dac_rst (dac_rst),
.dac_sync (dac_sync_out),
.dac_frame (),
.dac_clksel (dac_clksel),
.dac_par_type (),
.dac_par_enb (),
.dac_r1_mode (dac_r1_mode),