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DAQ1: Add missing clock line for the AD9250 ADC 

Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
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Paul Cercueil 2014-10-08 10:50:09 +02:00
parent 94e9396557
commit 9798704cc4
1 changed files with 1 additions and 1 deletions
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projects/daq1/common/daq1_bd.tcl
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@ -153,7 +153,7 @@ connect_bd_net -net axi_daq1_gt_rx_ip_sync [get_bd_pins axi_daq1_gt/rx_ip
connect_bd_net -net axi_daq1_gt_rx_ip_sof [get_bd_pins axi_daq1_gt/rx_ip_sof] [get_bd_pins axi_ad9250_jesd/rx_start_of_frame] connect_bd_net -net axi_daq1_gt_rx_ip_sof [get_bd_pins axi_daq1_gt/rx_ip_sof] [get_bd_pins axi_ad9250_jesd/rx_start_of_frame]
connect_bd_net -net axi_daq1_gt_rx_ip_data [get_bd_pins axi_daq1_gt/rx_ip_data] [get_bd_pins axi_ad9250_jesd/rx_tdata] connect_bd_net -net axi_daq1_gt_rx_ip_data [get_bd_pins axi_daq1_gt/rx_ip_data] [get_bd_pins axi_ad9250_jesd/rx_tdata]
connect_bd_net -net axi_daq1_gt_rx_data [get_bd_pins axi_daq1_gt/rx_data] [get_bd_pins axi_ad9250_core/rx_data] connect_bd_net -net axi_daq1_gt_rx_data [get_bd_pins axi_daq1_gt/rx_data] [get_bd_pins axi_ad9250_core/rx_data]
connect_bd_net -net axi_ad9250_adc_clk [get_bd_pins axi_ad9250_core/adc_clk] [get_bd_pins axi_ad9250_dma/fifo_wr_clk] connect_bd_net -net axi_ad9250_adc_clk [get_bd_pins axi_ad9250_core/adc_clk] [get_bd_pins axi_ad9250_dma/fifo_wr_clk] [get_bd_ports adc_clk]
connect_bd_net -net axi_ad9250_adc_enable_a [get_bd_pins axi_ad9250_core/adc_enable_a] [get_bd_ports adc_enable_a] connect_bd_net -net axi_ad9250_adc_enable_a [get_bd_pins axi_ad9250_core/adc_enable_a] [get_bd_ports adc_enable_a]
connect_bd_net -net axi_ad9250_adc_valid_a [get_bd_pins axi_ad9250_core/adc_valid_a] [get_bd_ports adc_valid_a] connect_bd_net -net axi_ad9250_adc_valid_a [get_bd_pins axi_ad9250_core/adc_valid_a] [get_bd_ports adc_valid_a]
connect_bd_net -net axi_ad9250_adc_data_a [get_bd_pins axi_ad9250_core/adc_data_a] [get_bd_ports adc_data_a] connect_bd_net -net axi_ad9250_adc_data_a [get_bd_pins axi_ad9250_core/adc_data_a] [get_bd_ports adc_data_a]