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A10GX: Update DDR3 configuration

main
Adrian Costina 2017-07-27 12:38:14 +01:00
parent 6a84b8b5a1
commit 977d730134
1 changed files with 5 additions and 0 deletions
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5
projects/common/a10gx/a10gx_system_qsys.tcl
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@ -65,6 +65,11 @@ set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_TRCD_NS} {13.09}
set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_TRP_NS} {13.09} set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_TRP_NS} {13.09}
set_instance_parameter_value sys_ddr3_cntrl {BOARD_DDR3_USER_RCLK_SLEW_RATE} {5.0} set_instance_parameter_value sys_ddr3_cntrl {BOARD_DDR3_USER_RCLK_SLEW_RATE} {5.0}
set_instance_parameter_value sys_ddr3_cntrl {SHORT_QSYS_INTERFACE_NAMES} {1} set_instance_parameter_value sys_ddr3_cntrl {SHORT_QSYS_INTERFACE_NAMES} {1}
set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_RTT_NOM_ENUM} {DDR3_RTT_NOM_RZQ_2}
set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_RTT_WR_ENUM} {DDR3_RTT_WR_ODT_DISABLED}
set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_TRRD_CYC} {7}
set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_TFAW_NS} {35.0}
set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_TRFC_NS} {260.0}
add_connection sys_clk.clk_reset sys_ddr3_cntrl.global_reset_n add_connection sys_clk.clk_reset sys_ddr3_cntrl.global_reset_n
add_interface sys_ddr3_cntrl_mem conduit end add_interface sys_ddr3_cntrl_mem conduit end
add_interface sys_ddr3_cntrl_oct conduit end add_interface sys_ddr3_cntrl_oct conduit end