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jesd204:up_common: Add a synthesis register for NUM_LINKS

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Istvan Csomortani 2018-04-04 12:44:57 +01:00 committed by István Csomortáni
parent e71f9e384e
commit 974131cfc5
2 changed files with 3 additions and 1 deletions
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3
library/jesd204/axi_jesd204_common/jesd204_up_common.v
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@ -212,7 +212,8 @@ always @(*) begin
/* Core configuration */
12'h004: up_rdata <= NUM_LANES;
12'h005: up_rdata <= DATA_PATH_WIDTH;
/* 0x06-0x0f reserved for future use */
12'h006: up_rdata <= {24'b0, NUM_LINKS[7:0]};
/* 0x07-0x0f reserved for future use */
/* 0x10-0x1f reserved for core specific HDL configuration information */
/* IRQ block */

1
library/jesd204/tb/axi_jesd204_rx_regmap_tb.v
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@ -160,6 +160,7 @@ module axi_jesd204_rx_tb;
set_reset_reg_value('h00, 32'h00010061); /* PCORE version register */
set_reset_reg_value('h0c, 32'h32303452); /* PCORE magic register */
set_reset_reg_value('h10, NUM_LANES); /* Number of lanes */
set_reset_reg_value('h18, NUM_LINKS); /* Number of links */
set_reset_reg_value('h40, 32'h00000100); /* Elastic buffer size */
set_reset_reg_value('h14, 'h2); /* Datapath width */
set_reset_reg_value('hc0, 'h1); /* Core reset */