diff --git a/library/jesd204/axi_jesd204_common/jesd204_up_common.v b/library/jesd204/axi_jesd204_common/jesd204_up_common.v
index 46f326a7c..a11d3a6c4 100644
--- a/library/jesd204/axi_jesd204_common/jesd204_up_common.v
+++ b/library/jesd204/axi_jesd204_common/jesd204_up_common.v
@@ -212,7 +212,8 @@ always @(*) begin
   /* Core configuration */
   12'h004: up_rdata <= NUM_LANES;
   12'h005: up_rdata <= DATA_PATH_WIDTH;
-  /* 0x06-0x0f reserved for future use */
+  12'h006: up_rdata <= {24'b0, NUM_LINKS[7:0]};
+  /* 0x07-0x0f reserved for future use */
   /* 0x10-0x1f reserved for core specific HDL configuration information */
 
   /* IRQ block */
diff --git a/library/jesd204/tb/axi_jesd204_rx_regmap_tb.v b/library/jesd204/tb/axi_jesd204_rx_regmap_tb.v
index a6bdac086..94590ea8f 100644
--- a/library/jesd204/tb/axi_jesd204_rx_regmap_tb.v
+++ b/library/jesd204/tb/axi_jesd204_rx_regmap_tb.v
@@ -160,6 +160,7 @@ module axi_jesd204_rx_tb;
     set_reset_reg_value('h00, 32'h00010061); /* PCORE version register */
     set_reset_reg_value('h0c, 32'h32303452); /* PCORE magic register */
     set_reset_reg_value('h10, NUM_LANES); /* Number of lanes */
+    set_reset_reg_value('h18, NUM_LINKS); /* Number of links */
     set_reset_reg_value('h40, 32'h00000100); /* Elastic buffer size */
     set_reset_reg_value('h14, 'h2); /* Datapath width */
     set_reset_reg_value('hc0, 'h1); /* Core reset */