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fmcomms1: Remove project

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AndreiGrozav 2017-02-03 16:42:44 +02:00
parent 096274a033
commit 971bcbb0fc
32 changed files with 0 additions and 3208 deletions
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39
projects/fmcomms1/Makefile
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####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
.PHONY: all clean clean-all
all:
-make -C ac701 all
-make -C kc705 all
-make -C vc707 all
-make -C zc702 all
-make -C zc706 all
-make -C zed all
-make -C zc706 all
clean:
make -C ac701 clean
make -C kc705 clean
make -C vc707 clean
make -C zc702 clean
make -C zc706 clean
make -C zed clean
make -C zc706 clean
clean-all:
make -C ac701 clean-all
make -C kc705 clean-all
make -C vc707 clean-all
make -C zc702 clean-all
make -C zc706 clean-all
make -C zed clean-all
make -C zc706 clean-all
####################################################################################
####################################################################################

76
projects/fmcomms1/ac701/Makefile
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####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS += system_top.v
M_DEPS += system_project.tcl
M_DEPS += system_constr.xdc
M_DEPS += system_bd.tcl
M_DEPS += ../common/fmcomms1_bd.tcl
M_DEPS += ../../scripts/adi_project.tcl
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_board.tcl
M_DEPS += ../../common/ac701/ac701_system_mig.prj
M_DEPS += ../../common/ac701/ac701_system_constr.xdc
M_DEPS += ../../common/ac701/ac701_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9122/axi_ad9122.xpr
M_DEPS += ../../../library/axi_ad9643/axi_ad9643.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.runs
M_FLIST += *.srcs
M_FLIST += *.sdk
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
M_FLIST += *.ip_user_files
.PHONY: all lib clean clean-all
all: lib fmcomms1_ac701.sdk/system_top.hdf
clean:
rm -rf $(M_FLIST)
clean-all:clean
make -C ../../../library/axi_ad9122 clean
make -C ../../../library/axi_ad9643 clean
make -C ../../../library/axi_dmac clean
make -C ../../../library/util_cpack clean
make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean
fmcomms1_ac701.sdk/system_top.hdf: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_VIVADO) system_project.tcl >> fmcomms1_ac701_vivado.log 2>&1
lib:
make -C ../../../library/axi_ad9122
make -C ../../../library/axi_ad9643
make -C ../../../library/axi_dmac
make -C ../../../library/util_cpack
make -C ../../../library/util_upack
make -C ../../../library/util_wfifo
####################################################################################
####################################################################################

5
projects/fmcomms1/ac701/system_bd.tcl
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source $ad_hdl_dir/projects/common/ac701/ac701_system_bd.tcl
source ../common/fmcomms1_bd.tcl
set_property -dict [list CONFIG.FIFO_SIZE {8}] $axi_ad9643_dma

158
projects/fmcomms1/ac701/system_constr.xdc
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# reference
set_property IOSTANDARD LVDS_25 [get_ports ref_clk_out_p]
set_property DIFF_TERM TRUE [get_ports ref_clk_out_p]
set_property PACKAGE_PIN J21 [get_ports ref_clk_out_n]
set_property IOSTANDARD LVDS_25 [get_ports ref_clk_out_n]
set_property DIFF_TERM TRUE [get_ports ref_clk_out_n]
# dac
set_property IOSTANDARD LVDS_25 [get_ports dac_clk_in_p]
set_property DIFF_TERM TRUE [get_ports dac_clk_in_p]
set_property PACKAGE_PIN C19 [get_ports dac_clk_in_n]
set_property IOSTANDARD LVDS_25 [get_ports dac_clk_in_n]
set_property DIFF_TERM TRUE [get_ports dac_clk_in_n]
set_property IOSTANDARD LVDS_25 [get_ports dac_clk_out_p]
set_property PACKAGE_PIN H19 [get_ports dac_clk_out_n]
set_property IOSTANDARD LVDS_25 [get_ports dac_clk_out_n]
set_property IOSTANDARD LVDS_25 [get_ports dac_frame_out_p]
set_property PACKAGE_PIN A19 [get_ports dac_frame_out_n]
set_property IOSTANDARD LVDS_25 [get_ports dac_frame_out_n]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[0]}]
set_property PACKAGE_PIN G26 [get_ports {dac_data_out_n[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[1]}]
set_property PACKAGE_PIN F25 [get_ports {dac_data_out_n[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[2]}]
set_property PACKAGE_PIN D25 [get_ports {dac_data_out_n[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[3]}]
set_property PACKAGE_PIN K23 [get_ports {dac_data_out_n[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[4]}]
set_property PACKAGE_PIN D26 [get_ports {dac_data_out_n[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[5]}]
set_property PACKAGE_PIN F24 [get_ports {dac_data_out_n[5]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[5]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[6]}]
set_property PACKAGE_PIN H18 [get_ports {dac_data_out_n[6]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[6]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[7]}]
set_property PACKAGE_PIN F22 [get_ports {dac_data_out_n[7]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[7]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[8]}]
set_property PACKAGE_PIN L18 [get_ports {dac_data_out_n[8]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[8]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[9]}]
set_property PACKAGE_PIN E23 [get_ports {dac_data_out_n[9]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[9]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[10]}]
set_property PACKAGE_PIN H24 [get_ports {dac_data_out_n[10]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[10]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[11]}]
set_property PACKAGE_PIN J20 [get_ports {dac_data_out_n[11]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[11]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[12]}]
set_property PACKAGE_PIN L14 [get_ports {dac_data_out_n[12]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[12]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[13]}]
set_property PACKAGE_PIN M17 [get_ports {dac_data_out_n[13]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[13]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[14]}]
set_property PACKAGE_PIN A22 [get_ports {dac_data_out_n[14]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[14]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[15]}]
set_property PACKAGE_PIN D21 [get_ports {dac_data_out_n[15]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[15]}]
# adc
set_property IOSTANDARD LVDS_25 [get_ports adc_clk_in_p]
set_property DIFF_TERM TRUE [get_ports adc_clk_in_p]
set_property PACKAGE_PIN H22 [get_ports adc_clk_in_n]
set_property IOSTANDARD LVDS_25 [get_ports adc_clk_in_n]
set_property DIFF_TERM TRUE [get_ports adc_clk_in_n]
set_property IOSTANDARD LVDS_25 [get_ports adc_or_in_p]
set_property DIFF_TERM TRUE [get_ports adc_or_in_p]
set_property PACKAGE_PIN C18 [get_ports adc_or_in_n]
set_property IOSTANDARD LVDS_25 [get_ports adc_or_in_n]
set_property DIFF_TERM TRUE [get_ports adc_or_in_n]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[0]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[0]}]
set_property PACKAGE_PIN G21 [get_ports {adc_data_in_n[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[0]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[1]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[1]}]
set_property PACKAGE_PIN B21 [get_ports {adc_data_in_n[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[1]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[2]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[2]}]
set_property PACKAGE_PIN A20 [get_ports {adc_data_in_n[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[2]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[3]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[3]}]
set_property PACKAGE_PIN F17 [get_ports {adc_data_in_n[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[3]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[4]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[4]}]
set_property PACKAGE_PIN F15 [get_ports {adc_data_in_n[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[4]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[5]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[5]}]
set_property PACKAGE_PIN A18 [get_ports {adc_data_in_n[5]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[5]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[5]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[6]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[6]}]
set_property PACKAGE_PIN D20 [get_ports {adc_data_in_n[6]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[6]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[6]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[7]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[7]}]
set_property PACKAGE_PIN G16 [get_ports {adc_data_in_n[7]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[7]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[7]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[8]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[8]}]
set_property PACKAGE_PIN H15 [get_ports {adc_data_in_n[8]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[8]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[8]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[9]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[9]}]
set_property PACKAGE_PIN F19 [get_ports {adc_data_in_n[9]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[9]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[9]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[10]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[10]}]
set_property PACKAGE_PIN D16 [get_ports {adc_data_in_n[10]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[10]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[10]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[11]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[11]}]
set_property PACKAGE_PIN B17 [get_ports {adc_data_in_n[11]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[11]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[11]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[12]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[12]}]
set_property PACKAGE_PIN F20 [get_ports {adc_data_in_n[12]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[12]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[12]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[13]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[13]}]
set_property PACKAGE_PIN E18 [get_ports {adc_data_in_n[13]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[13]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[13]}]
# clocks
create_clock -period 2.000 -name dac_clk_in [get_ports dac_clk_in_p]
create_clock -period 4.000 -name adc_clk_in [get_ports adc_clk_in_p]

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projects/fmcomms1/ac701/system_project.tcl
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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_create fmcomms1_ac701
adi_project_files fmcomms1_ac701 [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/ac701/ac701_system_constr.xdc" ]
set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/ac701/ac701_system_constr.xdc]
set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
adi_project_run fmcomms1_ac701

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projects/fmcomms1/ac701/system_top.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
sys_rst,
sys_clk_p,
sys_clk_n,
uart_sin,
uart_sout,
ddr3_addr,
ddr3_ba,
ddr3_cas_n,
ddr3_ck_n,
ddr3_ck_p,
ddr3_cke,
ddr3_cs_n,
ddr3_dm,
ddr3_dq,
ddr3_dqs_n,
ddr3_dqs_p,
ddr3_odt,
ddr3_ras_n,
ddr3_reset_n,
ddr3_we_n,
phy_reset_n,
phy_mdc,
phy_mdio,
phy_tx_clk,
phy_tx_ctrl,
phy_tx_data,
phy_rx_clk,
phy_rx_ctrl,
phy_rx_data,
fan_pwm,
gpio_lcd,
gpio_bd,
iic_rstn,
iic_scl,
iic_sda,
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_frame_out_p,
dac_frame_out_n,
dac_data_out_p,
dac_data_out_n,
adc_clk_in_p,
adc_clk_in_n,
adc_or_in_p,
adc_or_in_n,
adc_data_in_p,
adc_data_in_n,
ref_clk_out_p,
ref_clk_out_n);
input sys_rst;
input sys_clk_p;
input sys_clk_n;
input uart_sin;
output uart_sout;
output [13:0] ddr3_addr;
output [ 2:0] ddr3_ba;
output ddr3_cas_n;
output [ 0:0] ddr3_ck_n;
output [ 0:0] ddr3_ck_p;
output [ 0:0] ddr3_cke;
output [ 0:0] ddr3_cs_n;
output [ 7:0] ddr3_dm;
inout [63:0] ddr3_dq;
inout [ 7:0] ddr3_dqs_n;
inout [ 7:0] ddr3_dqs_p;
output [ 0:0] ddr3_odt;
output ddr3_ras_n;
output ddr3_reset_n;
output ddr3_we_n;
output phy_reset_n;
output phy_mdc;
inout phy_mdio;
output phy_tx_clk;
output phy_tx_ctrl;
output [ 3:0] phy_tx_data;
input phy_rx_clk;
input phy_rx_ctrl;
input [ 3:0] phy_rx_data;
output fan_pwm;
inout [ 6:0] gpio_lcd;
inout [12:0] gpio_bd;
output iic_rstn;
inout iic_scl;
inout iic_sda;
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output dac_frame_out_p;
output dac_frame_out_n;
output [15:0] dac_data_out_p;
output [15:0] dac_data_out_n;
input adc_clk_in_p;
input adc_clk_in_n;
input adc_or_in_p;
input adc_or_in_n;
input [13:0] adc_data_in_p;
input [13:0] adc_data_in_n;
output ref_clk_out_p;
output ref_clk_out_n;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire ref_clk;
wire oddr_ref_clk;
// assignments
assign mgt_clk_sel = 2'd0;
assign fan_pwm = 1'b1;
assign iic_rstn = 1'b1;
// instantiations
ad_iobuf #(.DATA_WIDTH(13)) i_iobuf_sw_led (
.dio_t (gpio_t[12:0]),
.dio_i (gpio_o[12:0]),
.dio_o (gpio_i[12:0]),
.dio_p (gpio_bd));
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
i_oddr_ref_clk (
.S (1'b0),
.CE (1'b1),
.R (1'b0),
.C (ref_clk),
.D1 (1'b1),
.D2 (1'b0),
.Q (oddr_ref_clk));
OBUFDS i_obufds_ref_clk (
.I (oddr_ref_clk),
.O (ref_clk_out_p),
.OB (ref_clk_out_n));
system_wrapper i_system_wrapper (
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.gpio_lcd_tri_io (gpio_lcd),
.gpio0_o (gpio_o[31:0]),
.gpio0_t (gpio_t[31:0]),
.gpio0_i (gpio_i[31:0]),
.gpio1_o (gpio_o[63:32]),
.gpio1_t (gpio_t[63:32]),
.gpio1_i (gpio_i[63:32]),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.mb_intr_06 (1'b0),
.mb_intr_07 (1'b0),
.mb_intr_08 (1'b0),
.mb_intr_14 (1'b0),
.mb_intr_15 (1'b0),
.adc_clk_in_n (adc_clk_in_n),
.adc_clk_in_p (adc_clk_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_or_in_n (adc_or_in_n),
.adc_or_in_p (adc_or_in_p),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_data_out_n (dac_data_out_n),
.dac_data_out_p (dac_data_out_p),
.dac_frame_out_n (dac_frame_out_n),
.dac_frame_out_p (dac_frame_out_p),
.ref_clk (ref_clk),
.mdio_mdio_io (phy_mdio),
.mdio_mdc (phy_mdc),
.phy_rst_n (phy_reset_n),
.rgmii_rd (phy_rx_data),
.rgmii_rx_ctl (phy_rx_ctrl),
.rgmii_rxc (phy_rx_clk),
.rgmii_td (phy_tx_data),
.rgmii_tx_ctl (phy_tx_ctrl),
.rgmii_txc (phy_tx_clk),
.sys_clk_n (sys_clk_n),
.sys_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.uart_sin (uart_sin),
.uart_sout (uart_sout));
endmodule
// ***************************************************************************
// ***************************************************************************

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projects/fmcomms1/common/fmcomms1_bd.tcl
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# dac interface
create_bd_port -dir I dac_clk_in_p
create_bd_port -dir I dac_clk_in_n
create_bd_port -dir O dac_clk_out_p
create_bd_port -dir O dac_clk_out_n
create_bd_port -dir O dac_frame_out_p
create_bd_port -dir O dac_frame_out_n
create_bd_port -dir O -from 15 -to 0 dac_data_out_p
create_bd_port -dir O -from 15 -to 0 dac_data_out_n
# adc interface
create_bd_port -dir I adc_clk_in_p
create_bd_port -dir I adc_clk_in_n
create_bd_port -dir I adc_or_in_p
create_bd_port -dir I adc_or_in_n
create_bd_port -dir I -from 13 -to 0 adc_data_in_p
create_bd_port -dir I -from 13 -to 0 adc_data_in_n
# reference clock
create_bd_port -dir O ref_clk
# dac peripherals
set axi_ad9122 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9122:1.0 axi_ad9122]
set axi_ad9122_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9122_dma]
set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9122_dma
set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9122_dma
set_property -dict [list CONFIG.FIFO_SIZE {16}] $axi_ad9122_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9122_dma
set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9122_dma
set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9122_dma
set_property -dict [list CONFIG.AXI_SLICE_SRC {1}] $axi_ad9122_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9122_dma
set util_upack_ad9122 [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_upack_ad9122]
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $util_upack_ad9122
set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_upack_ad9122
# adc peripherals
set axi_ad9643 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9643:1.0 axi_ad9643]
set axi_ad9643_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9643_dma]
set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9643_dma
set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9643_dma
set_property -dict [list CONFIG.FIFO_SIZE {16}] $axi_ad9643_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9643_dma
set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9643_dma
set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9643_dma
set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9643_dma
set_property -dict [list CONFIG.AXI_SLICE_SRC {1}] $axi_ad9643_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9643_dma
set util_cpack_ad9643 [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_cpack_ad9643]
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] $util_cpack_ad9643
set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_cpack_ad9643
set util_ad9643_adc_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_wfifo:1.0 util_ad9643_adc_fifo]
set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_ad9643_adc_fifo
set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $util_ad9643_adc_fifo
set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $util_ad9643_adc_fifo
set_property -dict [list CONFIG.DOUT_DATA_WIDTH {32}] $util_ad9643_adc_fifo
# reference clock
set refclk_clkgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 refclk_clkgen]
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {30} ] $refclk_clkgen
set_property -dict [list CONFIG.USE_PHASE_ALIGNMENT {false} ] $refclk_clkgen
set_property -dict [list CONFIG.JITTER_SEL {Min_O_Jitter} ] $refclk_clkgen
set_property -dict [list CONFIG.USE_LOCKED {false} ] $refclk_clkgen
set_property -dict [list CONFIG.USE_RESET {false} ] $refclk_clkgen
# reference clock connections
ad_connect sys_200m_clk refclk_clkgen/clk_in1
ad_connect ref_clk refclk_clkgen/clk_out1
# connections (dac)
ad_connect dac_clk axi_ad9122/dac_div_clk
ad_connect dac_clk axi_ad9122_dma/fifo_rd_clk
ad_connect dac_clk util_upack_ad9122/dac_clk
ad_connect dac_clk_in_p axi_ad9122/dac_clk_in_p
ad_connect dac_clk_in_n axi_ad9122/dac_clk_in_n
ad_connect dac_clk_out_p axi_ad9122/dac_clk_out_p
ad_connect dac_clk_out_n axi_ad9122/dac_clk_out_n
ad_connect dac_frame_out_p axi_ad9122/dac_frame_out_p
ad_connect dac_frame_out_n axi_ad9122/dac_frame_out_n
ad_connect dac_data_out_p axi_ad9122/dac_data_out_p
ad_connect dac_data_out_n axi_ad9122/dac_data_out_n
ad_connect axi_ad9122/dac_valid_0 util_upack_ad9122/dac_valid_0
ad_connect axi_ad9122/dac_enable_0 util_upack_ad9122/dac_enable_0
ad_connect axi_ad9122/dac_ddata_0 util_upack_ad9122/dac_data_0
ad_connect axi_ad9122/dac_valid_1 util_upack_ad9122/dac_valid_1
ad_connect axi_ad9122/dac_enable_1 util_upack_ad9122/dac_enable_1
ad_connect axi_ad9122/dac_ddata_1 util_upack_ad9122/dac_data_1
ad_connect axi_ad9122/dac_dunf axi_ad9122_dma/fifo_rd_underflow
ad_connect util_upack_ad9122/dac_valid axi_ad9122_dma/fifo_rd_en
ad_connect util_upack_ad9122/dac_data axi_ad9122_dma/fifo_rd_dout
ad_connect util_upack_ad9122/dac_sync axi_ad9122/dac_sync_in
# connections (adc)
ad_connect adc_clk axi_ad9643/adc_clk
ad_connect adc_clk util_ad9643_adc_fifo/din_clk
ad_connect sys_200m_clk util_cpack_ad9643/adc_clk
ad_connect sys_200m_clk axi_ad9643/delay_clk
ad_connect sys_200m_clk axi_ad9643_dma/fifo_wr_clk
ad_connect sys_200m_clk util_ad9643_adc_fifo/dout_clk
ad_connect adc_rst axi_ad9643/adc_rst
ad_connect adc_rst util_ad9643_adc_fifo/din_rst
ad_connect sys_cpu_resetn util_ad9643_adc_fifo/dout_rstn
ad_connect sys_cpu_reset util_cpack_ad9643/adc_rst
ad_connect adc_clk_in_p axi_ad9643/adc_clk_in_p
ad_connect adc_clk_in_n axi_ad9643/adc_clk_in_n
ad_connect adc_or_in_p axi_ad9643/adc_or_in_p
ad_connect adc_or_in_n axi_ad9643/adc_or_in_n
ad_connect adc_data_in_p axi_ad9643/adc_data_in_p
ad_connect adc_data_in_n axi_ad9643/adc_data_in_n
ad_connect axi_ad9643/adc_valid_0 util_ad9643_adc_fifo/din_valid_0
ad_connect axi_ad9643/adc_enable_0 util_ad9643_adc_fifo/din_enable_0
ad_connect axi_ad9643/adc_data_0 util_ad9643_adc_fifo/din_data_0
ad_connect axi_ad9643/adc_valid_1 util_ad9643_adc_fifo/din_valid_1
ad_connect axi_ad9643/adc_enable_1 util_ad9643_adc_fifo/din_enable_1
ad_connect axi_ad9643/adc_data_1 util_ad9643_adc_fifo/din_data_1
ad_connect util_ad9643_adc_fifo/dout_valid_0 util_cpack_ad9643/adc_valid_0
ad_connect util_ad9643_adc_fifo/dout_enable_0 util_cpack_ad9643/adc_enable_0
ad_connect util_ad9643_adc_fifo/dout_data_0 util_cpack_ad9643/adc_data_0
ad_connect util_ad9643_adc_fifo/dout_valid_1 util_cpack_ad9643/adc_valid_1
ad_connect util_ad9643_adc_fifo/dout_enable_1 util_cpack_ad9643/adc_enable_1
ad_connect util_ad9643_adc_fifo/dout_data_1 util_cpack_ad9643/adc_data_1
ad_connect util_ad9643_adc_fifo/din_ovf axi_ad9643/adc_dovf
ad_connect util_cpack_ad9643/adc_valid axi_ad9643_dma/fifo_wr_en
ad_connect util_cpack_ad9643/adc_sync axi_ad9643_dma/fifo_wr_sync
ad_connect util_cpack_ad9643/adc_data axi_ad9643_dma/fifo_wr_din
ad_connect util_ad9643_adc_fifo/dout_ovf axi_ad9643_dma/fifo_wr_overflow
ad_connect sys_cpu_resetn axi_ad9122_dma/m_src_axi_aresetn
ad_connect sys_cpu_resetn axi_ad9643_dma/m_dest_axi_aresetn
# address map
ad_cpu_interconnect 0x74200000 axi_ad9122
ad_cpu_interconnect 0x79020000 axi_ad9643
ad_cpu_interconnect 0x7c400000 axi_ad9643_dma
ad_cpu_interconnect 0x7c420000 axi_ad9122_dma
ad_mem_hp1_interconnect sys_200m_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect sys_200m_clk axi_ad9643_dma/m_dest_axi
ad_mem_hp2_interconnect sys_200m_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect sys_200m_clk axi_ad9122_dma/m_src_axi
# interrupts
ad_cpu_interrupt ps-12 mb-12 axi_ad9122_dma/irq
ad_cpu_interrupt ps-13 mb-13 axi_ad9643_dma/irq

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projects/fmcomms1/kc705/Makefile
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####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS += system_top.v
M_DEPS += system_project.tcl
M_DEPS += system_constr.xdc
M_DEPS += system_bd.tcl
M_DEPS += ../common/fmcomms1_bd.tcl
M_DEPS += ../../scripts/adi_project.tcl
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_board.tcl
M_DEPS += ../../common/kc705/kc705_system_mig.prj
M_DEPS += ../../common/kc705/kc705_system_constr.xdc
M_DEPS += ../../common/kc705/kc705_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9122/axi_ad9122.xpr
M_DEPS += ../../../library/axi_ad9643/axi_ad9643.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.runs
M_FLIST += *.srcs
M_FLIST += *.sdk
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
M_FLIST += *.ip_user_files
.PHONY: all lib clean clean-all
all: lib fmcomms1_kc705.sdk/system_top.hdf
clean:
rm -rf $(M_FLIST)
clean-all:clean
make -C ../../../library/axi_ad9122 clean
make -C ../../../library/axi_ad9643 clean
make -C ../../../library/axi_dmac clean
make -C ../../../library/util_cpack clean
make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean
fmcomms1_kc705.sdk/system_top.hdf: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_VIVADO) system_project.tcl >> fmcomms1_kc705_vivado.log 2>&1
lib:
make -C ../../../library/axi_ad9122
make -C ../../../library/axi_ad9643
make -C ../../../library/axi_dmac
make -C ../../../library/util_cpack
make -C ../../../library/util_upack
make -C ../../../library/util_wfifo
####################################################################################
####################################################################################

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projects/fmcomms1/kc705/system_bd.tcl
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source $ad_hdl_dir/projects/common/kc705/kc705_system_bd.tcl
source ../common/fmcomms1_bd.tcl

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projects/fmcomms1/kc705/system_constr.xdc
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# reference
set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_p] ; ## FMC_LPC_LA17_CC_P
set_property -dict {PACKAGE_PIN AC27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_n] ; ## FMC_LPC_LA17_CC_N
# dac
set_property -dict {PACKAGE_PIN AF22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_p] ; ## FMC_LPC_CLK0_M2C_P
set_property -dict {PACKAGE_PIN AG23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_n] ; ## FMC_LPC_CLK0_M2C_N
set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVDS_25} [get_ports dac_clk_out_p] ; ## FMC_LPC_LA21_P
set_property -dict {PACKAGE_PIN AG28 IOSTANDARD LVDS_25} [get_ports dac_clk_out_n] ; ## FMC_LPC_LA21_N
set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVDS_25} [get_ports dac_frame_out_p] ; ## FMC_LPC_LA11_P
set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVDS_25} [get_ports dac_frame_out_n] ; ## FMC_LPC_LA11_N
set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[0]] ; ## FMC_LPC_LA32_P
set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[0]] ; ## FMC_LPC_LA32_N
set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[1]] ; ## FMC_LPC_LA33_P
set_property -dict {PACKAGE_PIN AC30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[1]] ; ## FMC_LPC_LA33_N
set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[2]] ; ## FMC_LPC_LA30_P
set_property -dict {PACKAGE_PIN AB30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[2]] ; ## FMC_LPC_LA30_N
set_property -dict {PACKAGE_PIN AE30 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[3]] ; ## FMC_LPC_LA28_P
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[3]] ; ## FMC_LPC_LA28_N
set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[4]] ; ## FMC_LPC_LA31_P
set_property -dict {PACKAGE_PIN AE29 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[4]] ; ## FMC_LPC_LA31_N
set_property -dict {PACKAGE_PIN AE28 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[5]] ; ## FMC_LPC_LA29_P
set_property -dict {PACKAGE_PIN AF28 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[5]] ; ## FMC_LPC_LA29_N
set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[6]] ; ## FMC_LPC_LA24_P
set_property -dict {PACKAGE_PIN AH30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[6]] ; ## FMC_LPC_LA24_N
set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[7]] ; ## FMC_LPC_LA25_P
set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[7]] ; ## FMC_LPC_LA25_N
set_property -dict {PACKAGE_PIN AJ27 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[8]] ; ## FMC_LPC_LA22_P
set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[8]] ; ## FMC_LPC_LA22_N
set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[9]] ; ## FMC_LPC_LA27_P
set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[9]] ; ## FMC_LPC_LA27_N
set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[10]] ; ## FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[10]] ; ## FMC_LPC_LA26_N
set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[11]] ; ## FMC_LPC_LA23_P
set_property -dict {PACKAGE_PIN AH27 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[11]] ; ## FMC_LPC_LA23_N
set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[12]] ; ## FMC_LPC_LA19_P
set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[12]] ; ## FMC_LPC_LA19_N
set_property -dict {PACKAGE_PIN AF26 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[13]] ; ## FMC_LPC_LA20_P
set_property -dict {PACKAGE_PIN AF27 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[13]] ; ## FMC_LPC_LA20_N
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[14]] ; ## FMC_LPC_LA15_P
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[14]] ; ## FMC_LPC_LA15_N
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[15]] ; ## FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN AD22 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[15]] ; ## FMC_LPC_LA16_N
# adc
set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; ## FMC_LPC_CLK1_M2C_P
set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; ## FMC_LPC_CLK1_M2C_N
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_p] ; ## FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AE24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_n] ; ## FMC_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN AD27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ; ## FMC_LPC_LA18_CC_P
set_property -dict {PACKAGE_PIN AD28 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ; ## FMC_LPC_LA18_CC_N
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ; ## FMC_LPC_LA14_P
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ; ## FMC_LPC_LA14_N
set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ; ## FMC_LPC_LA13_P
set_property -dict {PACKAGE_PIN AC25 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ; ## FMC_LPC_LA13_N
set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ; ## FMC_LPC_LA03_P
set_property -dict {PACKAGE_PIN AH20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ; ## FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ; ## FMC_LPC_LA05_P
set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ; ## FMC_LPC_LA05_N
set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ; ## FMC_LPC_LA10_P
set_property -dict {PACKAGE_PIN AK25 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ; ## FMC_LPC_LA10_N
set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ; ## FMC_LPC_LA12_P
set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ; ## FMC_LPC_LA12_N
set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ; ## FMC_LPC_LA07_P
set_property -dict {PACKAGE_PIN AH25 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ; ## FMC_LPC_LA07_N
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[8]] ; ## FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN AF21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[8]] ; ## FMC_LPC_LA02_N
set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[9]] ; ## FMC_LPC_LA04_P
set_property -dict {PACKAGE_PIN AJ21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[9]] ; ## FMC_LPC_LA04_N
set_property -dict {PACKAGE_PIN AK23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[10]] ; ## FMC_LPC_LA09_P
set_property -dict {PACKAGE_PIN AK24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[10]] ; ## FMC_LPC_LA09_N
set_property -dict {PACKAGE_PIN AJ22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[11]] ; ## FMC_LPC_LA08_P
set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[11]] ; ## FMC_LPC_LA08_N
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[12]] ; ## FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN AK21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[12]] ; ## FMC_LPC_LA06_N
set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[13]] ; ## FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[13]] ; ## FMC_LPC_LA01_CC_N
# clocks
create_clock -name dac_clk_in -period 2.00 [get_ports dac_clk_in_p]
create_clock -name adc_clk_in -period 4.00 [get_ports adc_clk_in_p]

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projects/fmcomms1/kc705/system_project.tcl
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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_create fmcomms1_kc705
adi_project_files fmcomms1_kc705 [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc" ]
set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc]
set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
set_property is_enabled false [get_files *system_axi*_spi*.xdc]
adi_project_run fmcomms1_kc705

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projects/fmcomms1/kc705/system_top.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
sys_rst,
sys_clk_p,
sys_clk_n,
uart_sin,
uart_sout,
ddr3_1_n,
ddr3_1_p,
ddr3_reset_n,
ddr3_addr,
ddr3_ba,
ddr3_cas_n,
ddr3_ras_n,
ddr3_we_n,
ddr3_ck_n,
ddr3_ck_p,
ddr3_cke,
ddr3_cs_n,
ddr3_dm,
ddr3_dq,
ddr3_dqs_n,
ddr3_dqs_p,
ddr3_odt,
mdio_mdc,
mdio_mdio,
mii_rst_n,
mii_col,
mii_crs,
mii_rx_clk,
mii_rx_er,
mii_rx_dv,
mii_rxd,
mii_tx_clk,
mii_tx_en,
mii_txd,
linear_flash_addr,
linear_flash_adv_ldn,
linear_flash_ce_n,
linear_flash_dq_io,
linear_flash_oen,
linear_flash_wen,
fan_pwm,
gpio_lcd,
gpio_bd,
iic_rstn,
iic_scl,
iic_sda,
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_frame_out_p,
dac_frame_out_n,
dac_data_out_p,
dac_data_out_n,
adc_clk_in_p,
adc_clk_in_n,
adc_or_in_p,
adc_or_in_n,
adc_data_in_p,
adc_data_in_n,
ref_clk_out_p,
ref_clk_out_n);
input sys_rst;
input sys_clk_p;
input sys_clk_n;
input uart_sin;
output uart_sout;
output [ 2:0] ddr3_1_n;
output [ 1:0] ddr3_1_p;
output ddr3_reset_n;
output [13:0] ddr3_addr;
output [ 2:0] ddr3_ba;
output ddr3_cas_n;
output ddr3_ras_n;
output ddr3_we_n;
output [ 0:0] ddr3_ck_n;
output [ 0:0] ddr3_ck_p;
output [ 0:0] ddr3_cke;
output [ 0:0] ddr3_cs_n;
output [ 7:0] ddr3_dm;
inout [63:0] ddr3_dq;
inout [ 7:0] ddr3_dqs_n;
inout [ 7:0] ddr3_dqs_p;
output [ 0:0] ddr3_odt;
output mdio_mdc;
inout mdio_mdio;
output mii_rst_n;
input mii_col;
input mii_crs;
input mii_rx_clk;
input mii_rx_er;
input mii_rx_dv;
input [ 3:0] mii_rxd;
input mii_tx_clk;
output mii_tx_en;
output [ 3:0] mii_txd;
output [26:1] linear_flash_addr;
output linear_flash_adv_ldn;
output linear_flash_ce_n;
inout [15:0] linear_flash_dq_io;
output linear_flash_oen;
output linear_flash_wen;
output fan_pwm;
inout [ 6:0] gpio_lcd;
inout [16:0] gpio_bd;
output iic_rstn;
inout iic_scl;
inout iic_sda;
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output dac_frame_out_p;
output dac_frame_out_n;
output [15:0] dac_data_out_p;
output [15:0] dac_data_out_n;
input adc_clk_in_p;
input adc_clk_in_n;
input adc_or_in_p;
input adc_or_in_n;
input [13:0] adc_data_in_p;
input [13:0] adc_data_in_n;
output ref_clk_out_p;
output ref_clk_out_n;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 7:0] spi_csn;
wire spi_clk;
wire spi_mosi;
wire spi_miso;
wire ref_clk;
wire oddr_ref_clk;
// default logic
assign ddr3_1_p = 2'b11;
assign ddr3_1_n = 3'b000;
assign fan_pwm = 1'b1;
assign iic_rstn = 1'b1;
// instantiations
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
i_oddr_ref_clk (
.S (1'b0),
.CE (1'b1),
.R (1'b0),
.C (ref_clk),
.D1 (1'b1),
.D2 (1'b0),
.Q (oddr_ref_clk));
OBUFDS i_obufds_ref_clk (
.I (oddr_ref_clk),
.O (ref_clk_out_p),
.OB (ref_clk_out_n));
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf_bd (
.dio_t (gpio_t[16:0]),
.dio_i (gpio_o[16:0]),
.dio_o (gpio_i[16:0]),
.dio_p (gpio_bd));
system_wrapper i_system_wrapper (
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.gpio0_i (gpio_i[31:0]),
.gpio0_o (gpio_o[31:0]),
.gpio0_t (gpio_t[31:0]),
.gpio1_i (gpio_i[63:32]),
.gpio1_o (gpio_o[63:32]),
.gpio1_t (gpio_t[63:32]),
.gpio_lcd_tri_io (gpio_lcd),
.adc_clk_in_n (adc_clk_in_n),
.adc_clk_in_p (adc_clk_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_or_in_n (adc_or_in_n),
.adc_or_in_p (adc_or_in_p),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_data_out_n (dac_data_out_n),
.dac_data_out_p (dac_data_out_p),
.dac_frame_out_n (dac_frame_out_n),
.dac_frame_out_p (dac_frame_out_p),
.ref_clk (ref_clk),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.mb_intr_02 (1'd0),
.mb_intr_03 (1'd0),
.mb_intr_06 (1'd0),
.mb_intr_07 (1'd0),
.mb_intr_08 (1'd0),
.mb_intr_14 (1'd0),
.mb_intr_15 (1'd0),
.mdio_mdc (mdio_mdc),
.mdio_mdio_io (mdio_mdio),
.mii_col (mii_col),
.mii_crs (mii_crs),
.mii_rst_n (mii_rst_n),
.mii_rx_clk (mii_rx_clk),
.mii_rx_dv (mii_rx_dv),
.mii_rx_er (mii_rx_er),
.mii_rxd (mii_rxd),
.mii_tx_clk (mii_tx_clk),
.mii_tx_en (mii_tx_en),
.mii_txd (mii_txd),
.linear_flash_addr (linear_flash_addr),
.linear_flash_adv_ldn (linear_flash_adv_ldn),
.linear_flash_ce_n (linear_flash_ce_n),
.linear_flash_dq_io (linear_flash_dq_io),
.linear_flash_oen (linear_flash_oen),
.linear_flash_wen (linear_flash_wen),
.spi_clk_i (spi_clk),
.spi_clk_o (spi_clk),
.spi_csn_i (spi_csn),
.spi_csn_o (spi_csn),
.spi_sdi_i (spi_miso),
.spi_sdo_i (spi_mosi),
.spi_sdo_o (spi_mosi),
.sys_clk_n (sys_clk_n),
.sys_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.uart_sin (uart_sin),
.uart_sout (uart_sout));
endmodule
// ***************************************************************************
// ***************************************************************************

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projects/fmcomms1/vc707/Makefile
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####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS += system_top.v
M_DEPS += system_project.tcl
M_DEPS += system_constr.xdc
M_DEPS += system_bd.tcl
M_DEPS += ../common/fmcomms1_bd.tcl
M_DEPS += ../../scripts/adi_project.tcl
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_board.tcl
M_DEPS += ../../common/vc707/vc707_system_mig.prj
M_DEPS += ../../common/vc707/vc707_system_constr.xdc
M_DEPS += ../../common/vc707/vc707_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9122/axi_ad9122.xpr
M_DEPS += ../../../library/axi_ad9643/axi_ad9643.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.runs
M_FLIST += *.srcs
M_FLIST += *.sdk
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
M_FLIST += *.ip_user_files
.PHONY: all lib clean clean-all
all: lib fmcomms1_vc707.sdk/system_top.hdf
clean:
rm -rf $(M_FLIST)
clean-all:clean
make -C ../../../library/axi_ad9122 clean
make -C ../../../library/axi_ad9643 clean
make -C ../../../library/axi_dmac clean
make -C ../../../library/util_cpack clean
make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean
fmcomms1_vc707.sdk/system_top.hdf: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_VIVADO) system_project.tcl >> fmcomms1_vc707_vivado.log 2>&1
lib:
make -C ../../../library/axi_ad9122
make -C ../../../library/axi_ad9643
make -C ../../../library/axi_dmac
make -C ../../../library/util_cpack
make -C ../../../library/util_upack
make -C ../../../library/util_wfifo
####################################################################################
####################################################################################

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projects/fmcomms1/vc707/system_bd.tcl
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source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
source ../common/fmcomms1_bd.tcl

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projects/fmcomms1/vc707/system_constr.xdc
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# reference
set_property -dict {PACKAGE_PIN U37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports ref_clk_out_p] ; ## FMC_LPC_LA17_CC_P
set_property -dict {PACKAGE_PIN U38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports ref_clk_out_n] ; ## FMC_LPC_LA17_CC_N
# dac
set_property -dict {PACKAGE_PIN AF39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports dac_clk_in_p] ; ## FMC_LPC_CLK0_M2C_P
set_property -dict {PACKAGE_PIN AF40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports dac_clk_in_n] ; ## FMC_LPC_CLK0_M2C_N
set_property -dict {PACKAGE_PIN P35 IOSTANDARD LVDS} [get_ports dac_clk_out_p] ; ## FMC_LPC_LA21_P
set_property -dict {PACKAGE_PIN P36 IOSTANDARD LVDS} [get_ports dac_clk_out_n] ; ## FMC_LPC_LA21_N
set_property -dict {PACKAGE_PIN Y42 IOSTANDARD LVDS} [get_ports dac_frame_out_p] ; ## FMC_LPC_LA11_P
set_property -dict {PACKAGE_PIN AA42 IOSTANDARD LVDS} [get_ports dac_frame_out_n] ; ## FMC_LPC_LA11_N
set_property -dict {PACKAGE_PIN P37 IOSTANDARD LVDS} [get_ports dac_data_out_p[0]] ; ## FMC_LPC_LA32_P
set_property -dict {PACKAGE_PIN P38 IOSTANDARD LVDS} [get_ports dac_data_out_n[0]] ; ## FMC_LPC_LA32_N
set_property -dict {PACKAGE_PIN T36 IOSTANDARD LVDS} [get_ports dac_data_out_p[1]] ; ## FMC_LPC_LA33_P
set_property -dict {PACKAGE_PIN R37 IOSTANDARD LVDS} [get_ports dac_data_out_n[1]] ; ## FMC_LPC_LA33_N
set_property -dict {PACKAGE_PIN T32 IOSTANDARD LVDS} [get_ports dac_data_out_p[2]] ; ## FMC_LPC_LA30_P
set_property -dict {PACKAGE_PIN R32 IOSTANDARD LVDS} [get_ports dac_data_out_n[2]] ; ## FMC_LPC_LA30_N
set_property -dict {PACKAGE_PIN V35 IOSTANDARD LVDS} [get_ports dac_data_out_p[3]] ; ## FMC_LPC_LA28_P
set_property -dict {PACKAGE_PIN V36 IOSTANDARD LVDS} [get_ports dac_data_out_n[3]] ; ## FMC_LPC_LA28_N
set_property -dict {PACKAGE_PIN V39 IOSTANDARD LVDS} [get_ports dac_data_out_p[4]] ; ## FMC_LPC_LA31_P
set_property -dict {PACKAGE_PIN V40 IOSTANDARD LVDS} [get_ports dac_data_out_n[4]] ; ## FMC_LPC_LA31_N
set_property -dict {PACKAGE_PIN W36 IOSTANDARD LVDS} [get_ports dac_data_out_p[5]] ; ## FMC_LPC_LA29_P
set_property -dict {PACKAGE_PIN W37 IOSTANDARD LVDS} [get_ports dac_data_out_n[5]] ; ## FMC_LPC_LA29_N
set_property -dict {PACKAGE_PIN U34 IOSTANDARD LVDS} [get_ports dac_data_out_p[6]] ; ## FMC_LPC_LA24_P
set_property -dict {PACKAGE_PIN T35 IOSTANDARD LVDS} [get_ports dac_data_out_n[6]] ; ## FMC_LPC_LA24_N
set_property -dict {PACKAGE_PIN R33 IOSTANDARD LVDS} [get_ports dac_data_out_p[7]] ; ## FMC_LPC_LA25_P
set_property -dict {PACKAGE_PIN R34 IOSTANDARD LVDS} [get_ports dac_data_out_n[7]] ; ## FMC_LPC_LA25_N
set_property -dict {PACKAGE_PIN W32 IOSTANDARD LVDS} [get_ports dac_data_out_p[8]] ; ## FMC_LPC_LA22_P
set_property -dict {PACKAGE_PIN W33 IOSTANDARD LVDS} [get_ports dac_data_out_n[8]] ; ## FMC_LPC_LA22_N
set_property -dict {PACKAGE_PIN P32 IOSTANDARD LVDS} [get_ports dac_data_out_p[9]] ; ## FMC_LPC_LA27_P
set_property -dict {PACKAGE_PIN P33 IOSTANDARD LVDS} [get_ports dac_data_out_n[9]] ; ## FMC_LPC_LA27_N
set_property -dict {PACKAGE_PIN N33 IOSTANDARD LVDS} [get_ports dac_data_out_p[10]] ; ## FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN N34 IOSTANDARD LVDS} [get_ports dac_data_out_n[10]] ; ## FMC_LPC_LA26_N
set_property -dict {PACKAGE_PIN R38 IOSTANDARD LVDS} [get_ports dac_data_out_p[11]] ; ## FMC_LPC_LA23_P
set_property -dict {PACKAGE_PIN R39 IOSTANDARD LVDS} [get_ports dac_data_out_n[11]] ; ## FMC_LPC_LA23_N
set_property -dict {PACKAGE_PIN U32 IOSTANDARD LVDS} [get_ports dac_data_out_p[12]] ; ## FMC_LPC_LA19_P
set_property -dict {PACKAGE_PIN U33 IOSTANDARD LVDS} [get_ports dac_data_out_n[12]] ; ## FMC_LPC_LA19_N
set_property -dict {PACKAGE_PIN V33 IOSTANDARD LVDS} [get_ports dac_data_out_p[13]] ; ## FMC_LPC_LA20_P
set_property -dict {PACKAGE_PIN V34 IOSTANDARD LVDS} [get_ports dac_data_out_n[13]] ; ## FMC_LPC_LA20_N
set_property -dict {PACKAGE_PIN AC38 IOSTANDARD LVDS} [get_ports dac_data_out_p[14]] ; ## FMC_LPC_LA15_P
set_property -dict {PACKAGE_PIN AC39 IOSTANDARD LVDS} [get_ports dac_data_out_n[14]] ; ## FMC_LPC_LA15_N
set_property -dict {PACKAGE_PIN AJ40 IOSTANDARD LVDS} [get_ports dac_data_out_p[15]] ; ## FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN AJ41 IOSTANDARD LVDS} [get_ports dac_data_out_n[15]] ; ## FMC_LPC_LA16_N
# adc
set_property -dict {PACKAGE_PIN U39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; ## FMC_LPC_CLK1_M2C_P
set_property -dict {PACKAGE_PIN T39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; ## FMC_LPC_CLK1_M2C_N
set_property -dict {PACKAGE_PIN AD40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_or_in_p] ; ## FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AD41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_or_in_n] ; ## FMC_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN U36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ; ## FMC_LPC_LA18_CC_P
set_property -dict {PACKAGE_PIN T37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ; ## FMC_LPC_LA18_CC_N
set_property -dict {PACKAGE_PIN AB38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ; ## FMC_LPC_LA14_P
set_property -dict {PACKAGE_PIN AB39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ; ## FMC_LPC_LA14_N
set_property -dict {PACKAGE_PIN W40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ; ## FMC_LPC_LA13_P
set_property -dict {PACKAGE_PIN Y40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ; ## FMC_LPC_LA13_N
set_property -dict {PACKAGE_PIN AJ42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ; ## FMC_LPC_LA03_P
set_property -dict {PACKAGE_PIN AK42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ; ## FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN AF42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ; ## FMC_LPC_LA05_P
set_property -dict {PACKAGE_PIN AG42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ; ## FMC_LPC_LA05_N
set_property -dict {PACKAGE_PIN AB41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ; ## FMC_LPC_LA10_P
set_property -dict {PACKAGE_PIN AB42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ; ## FMC_LPC_LA10_N
set_property -dict {PACKAGE_PIN Y39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ; ## FMC_LPC_LA12_P
set_property -dict {PACKAGE_PIN AA39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ; ## FMC_LPC_LA12_N
set_property -dict {PACKAGE_PIN AC40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ; ## FMC_LPC_LA07_P
set_property -dict {PACKAGE_PIN AC41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ; ## FMC_LPC_LA07_N
set_property -dict {PACKAGE_PIN AK39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[8]] ; ## FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN AL39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[8]] ; ## FMC_LPC_LA02_N
set_property -dict {PACKAGE_PIN AL41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[9]] ; ## FMC_LPC_LA04_P
set_property -dict {PACKAGE_PIN AL42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[9]] ; ## FMC_LPC_LA04_N
set_property -dict {PACKAGE_PIN AJ38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[10]] ; ## FMC_LPC_LA09_P
set_property -dict {PACKAGE_PIN AK38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[10]] ; ## FMC_LPC_LA09_N
set_property -dict {PACKAGE_PIN AD42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[11]] ; ## FMC_LPC_LA08_P
set_property -dict {PACKAGE_PIN AE42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[11]] ; ## FMC_LPC_LA08_N
set_property -dict {PACKAGE_PIN AD38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[12]] ; ## FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN AE38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[12]] ; ## FMC_LPC_LA06_N
set_property -dict {PACKAGE_PIN AF41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[13]] ; ## FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AG41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[13]] ; ## FMC_LPC_LA01_CC_N
# clocks
create_clock -name dac_clk_in -period 2.00 [get_ports dac_clk_in_p]
create_clock -name adc_clk_in -period 4.00 [get_ports adc_clk_in_p]

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projects/fmcomms1/vc707/system_project.tcl
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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_create fmcomms1_vc707
adi_project_files fmcomms1_vc707 [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc]
set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
adi_project_run fmcomms1_vc707

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projects/fmcomms1/vc707/system_top.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
sys_rst,
sys_clk_p,
sys_clk_n,
uart_sin,
uart_sout,
ddr3_addr,
ddr3_ba,
ddr3_cas_n,
ddr3_ck_n,
ddr3_ck_p,
ddr3_cke,
ddr3_cs_n,
ddr3_dm,
ddr3_dq,
ddr3_dqs_n,
ddr3_dqs_p,
ddr3_odt,
ddr3_ras_n,
ddr3_reset_n,
ddr3_we_n,
sgmii_rxp,
sgmii_rxn,
sgmii_txp,
sgmii_txn,
phy_rstn,
mgt_clk_p,
mgt_clk_n,
mdio_mdc,
mdio_mdio,
fan_pwm,
linear_flash_addr,
linear_flash_adv_ldn,
linear_flash_ce_n,
linear_flash_oen,
linear_flash_wen,
linear_flash_dq_io,
gpio_lcd,
gpio_bd,
iic_rstn,
iic_scl,
iic_sda,
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_frame_out_p,
dac_frame_out_n,
dac_data_out_p,
dac_data_out_n,
adc_clk_in_p,
adc_clk_in_n,
adc_or_in_p,
adc_or_in_n,
adc_data_in_p,
adc_data_in_n,
ref_clk_out_p,
ref_clk_out_n );
input sys_rst;
input sys_clk_p;
input sys_clk_n;
input uart_sin;
output uart_sout;
output [13:0] ddr3_addr;
output [ 2:0] ddr3_ba;
output ddr3_cas_n;
output [ 0:0] ddr3_ck_n;
output [ 0:0] ddr3_ck_p;
output [ 0:0] ddr3_cke;
output [ 0:0] ddr3_cs_n;
output [ 7:0] ddr3_dm;
inout [63:0] ddr3_dq;
inout [ 7:0] ddr3_dqs_n;
inout [ 7:0] ddr3_dqs_p;
output [ 0:0] ddr3_odt;
output ddr3_ras_n;
output ddr3_reset_n;
output ddr3_we_n;
input sgmii_rxp;
input sgmii_rxn;
output sgmii_txp;
output sgmii_txn;
output phy_rstn;
input mgt_clk_p;
input mgt_clk_n;
output mdio_mdc;
inout mdio_mdio;
output fan_pwm;
output [26:1] linear_flash_addr;
output linear_flash_adv_ldn;
output linear_flash_ce_n;
output linear_flash_oen;
output linear_flash_wen;
inout [15:0] linear_flash_dq_io;
inout [ 6:0] gpio_lcd;
inout [20:0] gpio_bd;
output iic_rstn;
inout iic_scl;
inout iic_sda;
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output dac_frame_out_p;
output dac_frame_out_n;
output [15:0] dac_data_out_p;
output [15:0] dac_data_out_n;
input adc_clk_in_p;
input adc_clk_in_n;
input adc_or_in_p;
input adc_or_in_n;
input [13:0] adc_data_in_p;
input [13:0] adc_data_in_n;
output ref_clk_out_p;
output ref_clk_out_n;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 7:0] spi_csn;
wire spi_clk;
wire spi_mosi;
wire spi_miso;
wire ref_clk;
wire oddr_ref_clk;
// assignments
assign fan_pwm = 1'b1;
assign iic_rstn = 1'b1;
// instantiations
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
i_oddr_ref_clk (
.S (1'b0),
.CE (1'b1),
.R (1'b0),
.C (ref_clk),
.D1 (1'b1),
.D2 (1'b0),
.Q (oddr_ref_clk));
OBUFDS i_obufds_ref_clk (
.I (oddr_ref_clk),
.O (ref_clk_out_p),
.OB (ref_clk_out_n));
ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_sw_led (
.dio_t (gpio_t[20:0]),
.dio_i (gpio_o[20:0]),
.dio_o (gpio_i[20:0]),
.dio_p (gpio_bd));
system_wrapper i_system_wrapper (
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.linear_flash_addr (linear_flash_addr),
.linear_flash_adv_ldn (linear_flash_adv_ldn),
.linear_flash_ce_n (linear_flash_ce_n),
.linear_flash_oen (linear_flash_oen),
.linear_flash_wen (linear_flash_wen),
.linear_flash_dq_io(linear_flash_dq_io),
.gpio0_i (gpio_i[31:0]),
.gpio0_o (gpio_o[31:0]),
.gpio0_t (gpio_t[31:0]),
.gpio1_i (gpio_i[63:32]),
.gpio1_o (gpio_o[63:32]),
.gpio1_t (gpio_t[63:32]),
.gpio_lcd_tri_io (gpio_lcd),
.adc_clk_in_n (adc_clk_in_n),
.adc_clk_in_p (adc_clk_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_or_in_n (adc_or_in_n),
.adc_or_in_p (adc_or_in_p),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_data_out_n (dac_data_out_n),
.dac_data_out_p (dac_data_out_p),
.dac_frame_out_n (dac_frame_out_n),
.dac_frame_out_p (dac_frame_out_p),
.ref_clk (ref_clk),
.mb_intr_06 (1'b0),
.mb_intr_07 (1'b0),
.mb_intr_08 (1'b0),
.mb_intr_14 (1'b0),
.mb_intr_15 (1'b0),
.mdio_mdc (mdio_mdc),
.mdio_mdio_io (mdio_mdio),
.mgt_clk_clk_n (mgt_clk_n),
.mgt_clk_clk_p (mgt_clk_p),
.phy_rstn (phy_rstn),
.phy_sd (1'b1),
.sgmii_rxn (sgmii_rxn),
.sgmii_rxp (sgmii_rxp),
.sgmii_txn (sgmii_txn),
.sgmii_txp (sgmii_txp),
.spi_clk_i (1'b0),
.spi_clk_o (spi_clk),
.spi_csn_i (8'hff),
.spi_csn_o (spi_csn),
.spi_sdi_i (spi_miso),
.spi_sdo_i (1'b0),
.spi_sdo_o (spi_mosi),
.sys_clk_n (sys_clk_n),
.sys_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.uart_sin (uart_sin),
.uart_sout (uart_sout));
endmodule
// ***************************************************************************
// ***************************************************************************

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####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS += system_top.v
M_DEPS += system_project.tcl
M_DEPS += system_constr.xdc
M_DEPS += system_bd.tcl
M_DEPS += ../common/fmcomms1_bd.tcl
M_DEPS += ../../scripts/adi_project.tcl
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_board.tcl
M_DEPS += ../../common/zc702/zc702_system_constr.xdc
M_DEPS += ../../common/zc702/zc702_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9122/axi_ad9122.xpr
M_DEPS += ../../../library/axi_ad9643/axi_ad9643.xpr
M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.runs
M_FLIST += *.srcs
M_FLIST += *.sdk
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
M_FLIST += *.ip_user_files
.PHONY: all lib clean clean-all
all: lib fmcomms1_zc702.sdk/system_top.hdf
clean:
rm -rf $(M_FLIST)
clean-all:clean
make -C ../../../library/axi_ad9122 clean
make -C ../../../library/axi_ad9643 clean
make -C ../../../library/axi_clkgen clean
make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_hdmi_tx clean
make -C ../../../library/axi_spdif_tx clean
make -C ../../../library/util_cpack clean
make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean
fmcomms1_zc702.sdk/system_top.hdf: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_VIVADO) system_project.tcl >> fmcomms1_zc702_vivado.log 2>&1
lib:
make -C ../../../library/axi_ad9122
make -C ../../../library/axi_ad9643
make -C ../../../library/axi_clkgen
make -C ../../../library/axi_dmac
make -C ../../../library/axi_hdmi_tx
make -C ../../../library/axi_spdif_tx
make -C ../../../library/util_cpack
make -C ../../../library/util_upack
make -C ../../../library/util_wfifo
####################################################################################
####################################################################################

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projects/fmcomms1/zc702/system_bd.tcl
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source $ad_hdl_dir/projects/common/zc702/zc702_system_bd.tcl
source ../common/fmcomms1_bd.tcl

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# reference
set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_p] ; ## FMC1_LPC_LA17_CC_P
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_n] ; ## FMC1_LPC_LA17_CC_N
# dac
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_p] ; ## FMC1_LPC_CLK0_M2C_P
set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_n] ; ## FMC1_LPC_CLK0_M2C_N
set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVDS_25} [get_ports dac_clk_out_p] ; ## FMC1_LPC_LA21_P
set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVDS_25} [get_ports dac_clk_out_n] ; ## FMC1_LPC_LA21_N
set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVDS_25} [get_ports dac_frame_out_p] ; ## FMC1_LPC_LA11_P
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVDS_25} [get_ports dac_frame_out_n] ; ## FMC1_LPC_LA11_N
set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[0]] ; ## FMC1_LPC_LA32_P
set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[0]] ; ## FMC1_LPC_LA32_N
set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[1]] ; ## FMC1_LPC_LA33_P
set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[1]] ; ## FMC1_LPC_LA33_N
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[2]] ; ## FMC1_LPC_LA30_P
set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[2]] ; ## FMC1_LPC_LA30_N
set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[3]] ; ## FMC1_LPC_LA28_P
set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[3]] ; ## FMC1_LPC_LA28_N
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[4]] ; ## FMC1_LPC_LA31_P
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[4]] ; ## FMC1_LPC_LA31_N
set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[5]] ; ## FMC1_LPC_LA29_P
set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[5]] ; ## FMC1_LPC_LA29_N
set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[6]] ; ## FMC1_LPC_LA24_P
set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[6]] ; ## FMC1_LPC_LA24_N
set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[7]] ; ## FMC1_LPC_LA25_P
set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[7]] ; ## FMC1_LPC_LA25_N
set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[8]] ; ## FMC1_LPC_LA22_P
set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[8]] ; ## FMC1_LPC_LA22_N
set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[9]] ; ## FMC1_LPC_LA27_P
set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[9]] ; ## FMC1_LPC_LA27_N
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[10]] ; ## FMC1_LPC_LA26_P
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[10]] ; ## FMC1_LPC_LA26_N
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[11]] ; ## FMC1_LPC_LA23_P
set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[11]] ; ## FMC1_LPC_LA23_N
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[12]] ; ## FMC1_LPC_LA19_P
set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[12]] ; ## FMC1_LPC_LA19_N
set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[13]] ; ## FMC1_LPC_LA20_P
set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[13]] ; ## FMC1_LPC_LA20_N
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[14]] ; ## FMC1_LPC_LA15_P
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[14]] ; ## FMC1_LPC_LA15_N
set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[15]] ; ## FMC1_LPC_LA16_P
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[15]] ; ## FMC1_LPC_LA16_N
# adc
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; ## FMC1_LPC_CLK1_M2C_P
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; ## FMC1_LPC_CLK1_M2C_N
set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_p] ; ## FMC1_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_n] ; ## FMC1_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ; ## FMC1_LPC_LA18_CC_P
set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ; ## FMC1_LPC_LA18_CC_N
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ; ## FMC1_LPC_LA14_P
set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ; ## FMC1_LPC_LA14_N
set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ; ## FMC1_LPC_LA13_P
set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ; ## FMC1_LPC_LA13_N
set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ; ## FMC1_LPC_LA03_P
set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ; ## FMC1_LPC_LA03_N
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ; ## FMC1_LPC_LA05_P
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ; ## FMC1_LPC_LA05_N
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ; ## FMC1_LPC_LA10_P
set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ; ## FMC1_LPC_LA10_N
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ; ## FMC1_LPC_LA12_P
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ; ## FMC1_LPC_LA12_N
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ; ## FMC1_LPC_LA07_P
set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ; ## FMC1_LPC_LA07_N
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[8]] ; ## FMC1_LPC_LA02_P
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[8]] ; ## FMC1_LPC_LA02_N
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[9]] ; ## FMC1_LPC_LA04_P
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[9]] ; ## FMC1_LPC_LA04_N
set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[10]] ; ## FMC1_LPC_LA09_P
set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[10]] ; ## FMC1_LPC_LA09_N
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[11]] ; ## FMC1_LPC_LA08_P
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[11]] ; ## FMC1_LPC_LA08_N
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[12]] ; ## FMC1_LPC_LA06_P
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[12]] ; ## FMC1_LPC_LA06_N
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[13]] ; ## FMC1_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[13]] ; ## FMC1_LPC_LA01_CC_N
# clocks
create_clock -name dac_clk_in -period 2.16 [get_ports dac_clk_in_p]
create_clock -name adc_clk_in -period 4.00 [get_ports adc_clk_in_p]

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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_create fmcomms1_zc702
adi_project_files fmcomms1_zc702 [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/zc702/zc702_system_constr.xdc" ]
set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc702/zc702_system_constr.xdc]
set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
adi_project_run fmcomms1_zc702

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projects/fmcomms1/zc702/system_top.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_frame_out_p,
dac_frame_out_n,
dac_data_out_p,
dac_data_out_n,
adc_clk_in_p,
adc_clk_in_n,
adc_or_in_p,
adc_or_in_n,
adc_data_in_p,
adc_data_in_n,
ref_clk_out_p,
ref_clk_out_n,
iic_scl,
iic_sda);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [15:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [15:0] hdmi_data;
output spdif;
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output dac_frame_out_p;
output dac_frame_out_n;
output [15:0] dac_data_out_p;
output [15:0] dac_data_out_n;
input adc_clk_in_p;
input adc_clk_in_n;
input adc_or_in_n;
input adc_or_in_p;
input [13:0] adc_data_in_n;
input [13:0] adc_data_in_p;
output ref_clk_out_p;
output ref_clk_out_n;
inout iic_scl;
inout iic_sda;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 2:0] spi0_csn;
wire spi0_clk;
wire spi0_mosi;
wire spi0_miso;
wire [ 2:0] spi1_csn;
wire spi1_clk;
wire spi1_mosi;
wire spi1_miso;
wire ref_clk;
wire oddr_ref_clk;
wire [15:0] ps_intrs;
// instantiations
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
i_oddr_ref_clk (
.S (1'b0),
.CE (1'b1),
.R (1'b0),
.C (ref_clk),
.D1 (1'b1),
.D2 (1'b0),
.Q (oddr_ref_clk));
OBUFDS i_obufds_ref_clk (
.I (oddr_ref_clk),
.O (ref_clk_out_p),
.OB (ref_clk_out_n));
ad_iobuf #(
.DATA_WIDTH(16))
i_gpio_bd (
.dio_t(gpio_t[15:0]),
.dio_i(gpio_o[15:0]),
.dio_o(gpio_i[15:0]),
.dio_p(gpio_bd));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.adc_clk_in_n (adc_clk_in_n),
.adc_clk_in_p (adc_clk_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_or_in_n (adc_or_in_n),
.adc_or_in_p (adc_or_in_p),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_data_out_n (dac_data_out_n),
.dac_data_out_p (dac_data_out_p),
.dac_frame_out_n (dac_frame_out_n),
.dac_frame_out_p (dac_frame_out_p),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.ref_clk (ref_clk),
.spdif (spdif),
.spi0_clk_i (spi0_clk),
.spi0_clk_o (spi0_clk),
.spi0_csn_0_o (spi0_csn[0]),
.spi0_csn_1_o (spi0_csn[1]),
.spi0_csn_2_o (spi0_csn[2]),
.spi0_csn_i (1'b1),
.spi0_sdi_i (spi0_miso),
.spi0_sdo_i (spi0_mosi),
.spi0_sdo_o (spi0_mosi),
.spi1_clk_i (spi1_clk),
.spi1_clk_o (spi1_clk),
.spi1_csn_0_o (spi1_csn[0]),
.spi1_csn_1_o (spi1_csn[1]),
.spi1_csn_2_o (spi1_csn[2]),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b1),
.spi1_sdo_i (spi1_mosi),
.spi1_sdo_o (spi1_mosi));
endmodule
// ***************************************************************************
// ***************************************************************************

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####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS += system_top.v
M_DEPS += system_project.tcl
M_DEPS += system_constr.xdc
M_DEPS += system_bd.tcl
M_DEPS += ../common/fmcomms1_bd.tcl
M_DEPS += ../../scripts/adi_project.tcl
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_board.tcl
M_DEPS += ../../common/zc706/zc706_system_constr.xdc
M_DEPS += ../../common/zc706/zc706_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9122/axi_ad9122.xpr
M_DEPS += ../../../library/axi_ad9643/axi_ad9643.xpr
M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.runs
M_FLIST += *.srcs
M_FLIST += *.sdk
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
M_FLIST += *.ip_user_files
.PHONY: all lib clean clean-all
all: lib fmcomms1_zc706.sdk/system_top.hdf
clean:
rm -rf $(M_FLIST)
clean-all:clean
make -C ../../../library/axi_ad9122 clean
make -C ../../../library/axi_ad9643 clean
make -C ../../../library/axi_clkgen clean
make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_hdmi_tx clean
make -C ../../../library/axi_spdif_tx clean
make -C ../../../library/util_cpack clean
make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean
fmcomms1_zc706.sdk/system_top.hdf: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_VIVADO) system_project.tcl >> fmcomms1_zc706_vivado.log 2>&1
lib:
make -C ../../../library/axi_ad9122
make -C ../../../library/axi_ad9643
make -C ../../../library/axi_clkgen
make -C ../../../library/axi_dmac
make -C ../../../library/axi_hdmi_tx
make -C ../../../library/axi_spdif_tx
make -C ../../../library/util_cpack
make -C ../../../library/util_upack
make -C ../../../library/util_wfifo
####################################################################################
####################################################################################

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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source ../common/fmcomms1_bd.tcl

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# reference
set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_p] ; ## FMC1_LPC_LA17_CC_P
set_property -dict {PACKAGE_PIN AC27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_n] ; ## FMC1_LPC_LA17_CC_N
# dac
set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_p] ; ## FMC1_LPC_CLK0_M2C_P
set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_n] ; ## FMC1_LPC_CLK0_M2C_N
set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVDS_25} [get_ports dac_clk_out_p] ; ## FMC1_LPC_LA21_P
set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVDS_25} [get_ports dac_clk_out_n] ; ## FMC1_LPC_LA21_N
set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVDS_25} [get_ports dac_frame_out_p] ; ## FMC1_LPC_LA11_P
set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVDS_25} [get_ports dac_frame_out_n] ; ## FMC1_LPC_LA11_N
set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[0]] ; ## FMC1_LPC_LA32_P
set_property -dict {PACKAGE_PIN Y27 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[0]] ; ## FMC1_LPC_LA32_N
set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[1]] ; ## FMC1_LPC_LA33_P
set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[1]] ; ## FMC1_LPC_LA33_N
set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[2]] ; ## FMC1_LPC_LA30_P
set_property -dict {PACKAGE_PIN AB30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[2]] ; ## FMC1_LPC_LA30_N
set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[3]] ; ## FMC1_LPC_LA28_P
set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[3]] ; ## FMC1_LPC_LA28_N
set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[4]] ; ## FMC1_LPC_LA31_P
set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[4]] ; ## FMC1_LPC_LA31_N
set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[5]] ; ## FMC1_LPC_LA29_P
set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[5]] ; ## FMC1_LPC_LA29_N
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[6]] ; ## FMC1_LPC_LA24_P
set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[6]] ; ## FMC1_LPC_LA24_N
set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[7]] ; ## FMC1_LPC_LA25_P
set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[7]] ; ## FMC1_LPC_LA25_N
set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[8]] ; ## FMC1_LPC_LA22_P
set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[8]] ; ## FMC1_LPC_LA22_N
set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[9]] ; ## FMC1_LPC_LA27_P
set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[9]] ; ## FMC1_LPC_LA27_N
set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[10]] ; ## FMC1_LPC_LA26_P
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[10]] ; ## FMC1_LPC_LA26_N
set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[11]] ; ## FMC1_LPC_LA23_P
set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[11]] ; ## FMC1_LPC_LA23_N
set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[12]] ; ## FMC1_LPC_LA19_P
set_property -dict {PACKAGE_PIN AH27 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[12]] ; ## FMC1_LPC_LA19_N
set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[13]] ; ## FMC1_LPC_LA20_P
set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[13]] ; ## FMC1_LPC_LA20_N
set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[14]] ; ## FMC1_LPC_LA15_P
set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[14]] ; ## FMC1_LPC_LA15_N
set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[15]] ; ## FMC1_LPC_LA16_P
set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[15]] ; ## FMC1_LPC_LA16_N
# adc
set_property -dict {PACKAGE_PIN AC28 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; ## FMC1_LPC_CLK1_M2C_P
set_property -dict {PACKAGE_PIN AD28 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; ## FMC1_LPC_CLK1_M2C_N
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_p] ; ## FMC1_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_n] ; ## FMC1_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN AE27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ; ## FMC1_LPC_LA18_CC_P
set_property -dict {PACKAGE_PIN AF27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ; ## FMC1_LPC_LA18_CC_N
set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ; ## FMC1_LPC_LA14_P
set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ; ## FMC1_LPC_LA14_N
set_property -dict {PACKAGE_PIN AH17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ; ## FMC1_LPC_LA13_P
set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ; ## FMC1_LPC_LA13_N
set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ; ## FMC1_LPC_LA03_P
set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ; ## FMC1_LPC_LA03_N
set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ; ## FMC1_LPC_LA05_P
set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ; ## FMC1_LPC_LA05_N
set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ; ## FMC1_LPC_LA10_P
set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ; ## FMC1_LPC_LA10_N
set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ; ## FMC1_LPC_LA12_P
set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ; ## FMC1_LPC_LA12_N
set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ; ## FMC1_LPC_LA07_P
set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ; ## FMC1_LPC_LA07_N
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[8]] ; ## FMC1_LPC_LA02_P
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[8]] ; ## FMC1_LPC_LA02_N
set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[9]] ; ## FMC1_LPC_LA04_P
set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[9]] ; ## FMC1_LPC_LA04_N
set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[10]] ; ## FMC1_LPC_LA09_P
set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[10]] ; ## FMC1_LPC_LA09_N
set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[11]] ; ## FMC1_LPC_LA08_P
set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[11]] ; ## FMC1_LPC_LA08_N
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[12]] ; ## FMC1_LPC_LA06_P
set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[12]] ; ## FMC1_LPC_LA06_N
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[13]] ; ## FMC1_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[13]] ; ## FMC1_LPC_LA01_CC_N
# clocks
create_clock -name dac_clk_in -period 2.00 [get_ports dac_clk_in_p]
create_clock -name adc_clk_in -period 4.00 [get_ports adc_clk_in_p]

18
projects/fmcomms1/zc706/system_project.tcl
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@ -1,18 +0,0 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_create fmcomms1_zc706
adi_project_files fmcomms1_zc706 [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc]
set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
adi_project_run fmcomms1_zc706

280
projects/fmcomms1/zc706/system_top.v
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@ -1,280 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_frame_out_p,
dac_frame_out_n,
dac_data_out_p,
dac_data_out_n,
adc_clk_in_p,
adc_clk_in_n,
adc_or_in_p,
adc_or_in_n,
adc_data_in_p,
adc_data_in_n,
ref_clk_out_p,
ref_clk_out_n,
iic_scl,
iic_sda);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [14:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [23:0] hdmi_data;
output spdif;
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output dac_frame_out_p;
output dac_frame_out_n;
output [15:0] dac_data_out_p;
output [15:0] dac_data_out_n;
input adc_clk_in_p;
input adc_clk_in_n;
input adc_or_in_p;
input adc_or_in_n;
input [13:0] adc_data_in_p;
input [13:0] adc_data_in_n;
output ref_clk_out_p;
output ref_clk_out_n;
inout iic_scl;
inout iic_sda;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 2:0] spi0_csn;
wire spi0_clk;
wire spi0_mosi;
wire spi0_miso;
wire [ 2:0] spi1_csn;
wire spi1_clk;
wire spi1_mosi;
wire spi1_miso;
wire ref_clk;
wire oddr_ref_clk;
// instantiations
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
i_oddr_ref_clk (
.S (1'b0),
.CE (1'b1),
.R (1'b0),
.C (ref_clk),
.D1 (1'b1),
.D2 (1'b0),
.Q (oddr_ref_clk));
OBUFDS i_obufds_ref_clk (
.I (oddr_ref_clk),
.O (ref_clk_out_p),
.OB (ref_clk_out_n));
ad_iobuf #(
.DATA_WIDTH(15))
i_gpio_bd (
.dio_t(gpio_t[14:0]),
.dio_i(gpio_o[14:0]),
.dio_o(gpio_i[14:0]),
.dio_p(gpio_bd));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.adc_clk_in_n (adc_clk_in_n),
.adc_clk_in_p (adc_clk_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_or_in_n (adc_or_in_n),
.adc_or_in_p (adc_or_in_p),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_data_out_n (dac_data_out_n),
.dac_data_out_p (dac_data_out_p),
.dac_frame_out_n (dac_frame_out_n),
.dac_frame_out_p (dac_frame_out_p),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.ref_clk (ref_clk),
.spdif (spdif),
.spi0_clk_i (spi0_clk),
.spi0_clk_o (spi0_clk),
.spi0_csn_0_o (spi0_csn[0]),
.spi0_csn_1_o (spi0_csn[1]),
.spi0_csn_2_o (spi0_csn[2]),
.spi0_csn_i (1'b1),
.spi0_sdi_i (spi0_miso),
.spi0_sdo_i (spi0_mosi),
.spi0_sdo_o (spi0_mosi),
.spi1_clk_i (spi1_clk),
.spi1_clk_o (spi1_clk),
.spi1_csn_0_o (spi1_csn[0]),
.spi1_csn_1_o (spi1_csn[1]),
.spi1_csn_2_o (spi1_csn[2]),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b1),
.spi1_sdo_i (spi1_mosi),
.spi1_sdo_o (spi1_mosi));
endmodule
// ***************************************************************************
// ***************************************************************************

90
projects/fmcomms1/zed/Makefile
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@ -1,90 +0,0 @@
####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS += system_top.v
M_DEPS += system_project.tcl
M_DEPS += system_constr.xdc
M_DEPS += system_bd.tcl
M_DEPS += ../common/fmcomms1_bd.tcl
M_DEPS += ../../scripts/adi_project.tcl
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_board.tcl
M_DEPS += ../../common/zed/zed_system_constr.xdc
M_DEPS += ../../common/zed/zed_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9122/axi_ad9122.xpr
M_DEPS += ../../../library/axi_ad9643/axi_ad9643.xpr
M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_i2c_mixer/util_i2c_mixer.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.runs
M_FLIST += *.srcs
M_FLIST += *.sdk
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
M_FLIST += *.ip_user_files
.PHONY: all lib clean clean-all
all: lib fmcomms1_zed.sdk/system_top.hdf
clean:
rm -rf $(M_FLIST)
clean-all:clean
make -C ../../../library/axi_ad9122 clean
make -C ../../../library/axi_ad9643 clean
make -C ../../../library/axi_clkgen clean
make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_hdmi_tx clean
make -C ../../../library/axi_i2s_adi clean
make -C ../../../library/axi_spdif_tx clean
make -C ../../../library/util_cpack clean
make -C ../../../library/util_i2c_mixer clean
make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean
fmcomms1_zed.sdk/system_top.hdf: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_VIVADO) system_project.tcl >> fmcomms1_zed_vivado.log 2>&1
lib:
make -C ../../../library/axi_ad9122
make -C ../../../library/axi_ad9643
make -C ../../../library/axi_clkgen
make -C ../../../library/axi_dmac
make -C ../../../library/axi_hdmi_tx
make -C ../../../library/axi_i2s_adi
make -C ../../../library/axi_spdif_tx
make -C ../../../library/util_cpack
make -C ../../../library/util_i2c_mixer
make -C ../../../library/util_upack
make -C ../../../library/util_wfifo
####################################################################################
####################################################################################

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projects/fmcomms1/zed/system_bd.tcl
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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
source ../common/fmcomms1_bd.tcl
# Add extra register slice between ADC DMA and HP1 to meet timing
#delete_bd_objs [get_bd_intf_nets axi_ad9643_dma_axi]
#create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_0
#set_property -dict [list CONFIG.REG_AW {0} CONFIG.REG_AR {0} CONFIG.REG_W {1} CONFIG.REG_R {0} CONFIG.REG_B {0}] [get_bd_cells axi_register_slice_0]
#ad_connect [get_bd_intf_pins axi_register_slice_0/S_AXI] [get_bd_intf_pins axi_ad9643_dma/m_dest_axi]
#connect_bd_intf_net [get_bd_intf_pins sys_ps7/S_AXI_HP1] [get_bd_intf_pins axi_register_slice_0/M_AXI]
#connect_bd_net -net [get_bd_nets sys_200m_clk] [get_bd_pins axi_register_slice_0/aclk] [get_bd_pins sys_ps7/FCLK_CLK1]
#connect_bd_net -net [get_bd_nets sys_100m_resetn] [get_bd_pins axi_register_slice_0/aresetn] [get_bd_pins sys_rstgen/peripheral_aresetn]
#assign_bd_address [get_bd_addr_segs {sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM }]

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projects/fmcomms1/zed/system_constr.xdc
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# reference
set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_p] ; ## FMC1_LPC_LA17_CC_P
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_n] ; ## FMC1_LPC_LA17_CC_N
# dac
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_p] ; ## FMC1_LPC_CLK0_M2C_P
set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_n] ; ## FMC1_LPC_CLK0_M2C_N
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVDS_25} [get_ports dac_clk_out_p] ; ## FMC1_LPC_LA21_P
set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVDS_25} [get_ports dac_clk_out_n] ; ## FMC1_LPC_LA21_N
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVDS_25} [get_ports dac_frame_out_p] ; ## FMC1_LPC_LA11_P
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVDS_25} [get_ports dac_frame_out_n] ; ## FMC1_LPC_LA11_N
set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[0]] ; ## FMC1_LPC_LA32_P
set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[0]] ; ## FMC1_LPC_LA32_N
set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[1]] ; ## FMC1_LPC_LA33_P
set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[1]] ; ## FMC1_LPC_LA33_N
set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[2]] ; ## FMC1_LPC_LA30_P
set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[2]] ; ## FMC1_LPC_LA30_N
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[3]] ; ## FMC1_LPC_LA28_P
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[3]] ; ## FMC1_LPC_LA28_N
set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[4]] ; ## FMC1_LPC_LA31_P
set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[4]] ; ## FMC1_LPC_LA31_N
set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[5]] ; ## FMC1_LPC_LA29_P
set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[5]] ; ## FMC1_LPC_LA29_N
set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[6]] ; ## FMC1_LPC_LA24_P
set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[6]] ; ## FMC1_LPC_LA24_N
set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[7]] ; ## FMC1_LPC_LA25_P
set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[7]] ; ## FMC1_LPC_LA25_N
set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[8]] ; ## FMC1_LPC_LA22_P
set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[8]] ; ## FMC1_LPC_LA22_N
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[9]] ; ## FMC1_LPC_LA27_P
set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[9]] ; ## FMC1_LPC_LA27_N
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[10]] ; ## FMC1_LPC_LA26_P
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[10]] ; ## FMC1_LPC_LA26_N
set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[11]] ; ## FMC1_LPC_LA23_P
set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[11]] ; ## FMC1_LPC_LA23_N
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[12]] ; ## FMC1_LPC_LA19_P
set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[12]] ; ## FMC1_LPC_LA19_N
set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[13]] ; ## FMC1_LPC_LA20_P
set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[13]] ; ## FMC1_LPC_LA20_N
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[14]] ; ## FMC1_LPC_LA15_P
set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[14]] ; ## FMC1_LPC_LA15_N
set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[15]] ; ## FMC1_LPC_LA16_P
set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[15]] ; ## FMC1_LPC_LA16_N
# adc
set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; ## FMC1_LPC_CLK1_M2C_P
set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; ## FMC1_LPC_CLK1_M2C_N
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_p] ; ## FMC1_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_n] ; ## FMC1_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ; ## FMC1_LPC_LA18_CC_P
set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ; ## FMC1_LPC_LA18_CC_N
set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ; ## FMC1_LPC_LA14_P
set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ; ## FMC1_LPC_LA14_N
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ; ## FMC1_LPC_LA13_P
set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ; ## FMC1_LPC_LA13_N
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ; ## FMC1_LPC_LA03_P
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ; ## FMC1_LPC_LA03_N
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ; ## FMC1_LPC_LA05_P
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ; ## FMC1_LPC_LA05_N
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ; ## FMC1_LPC_LA10_P
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ; ## FMC1_LPC_LA10_N
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ; ## FMC1_LPC_LA12_P
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ; ## FMC1_LPC_LA12_N
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ; ## FMC1_LPC_LA07_P
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ; ## FMC1_LPC_LA07_N
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[8]] ; ## FMC1_LPC_LA02_P
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[8]] ; ## FMC1_LPC_LA02_N
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[9]] ; ## FMC1_LPC_LA04_P
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[9]] ; ## FMC1_LPC_LA04_N
set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[10]] ; ## FMC1_LPC_LA09_P
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[10]] ; ## FMC1_LPC_LA09_N
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[11]] ; ## FMC1_LPC_LA08_P
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[11]] ; ## FMC1_LPC_LA08_N
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[12]] ; ## FMC1_LPC_LA06_P
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[12]] ; ## FMC1_LPC_LA06_N
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[13]] ; ## FMC1_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[13]] ; ## FMC1_LPC_LA01_CC_N
# clocks
create_clock -name dac_clk_in -period 2.16 [get_ports dac_clk_in_p]
create_clock -name adc_clk_in -period 4.00 [get_ports adc_clk_in_p]

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projects/fmcomms1/zed/system_project.tcl
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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_create fmcomms1_zed
adi_project_files fmcomms1_zed [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" ]
set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zed/zed_system_constr.xdc]
set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
adi_project_run fmcomms1_zed

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projects/fmcomms1/zed/system_top.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
i2s_mclk,
i2s_bclk,
i2s_lrclk,
i2s_sdata_out,
i2s_sdata_in,
spdif,
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_frame_out_p,
dac_frame_out_n,
dac_data_out_p,
dac_data_out_n,
adc_clk_in_p,
adc_clk_in_n,
adc_or_in_p,
adc_or_in_n,
adc_data_in_p,
adc_data_in_n,
ref_clk_out_p,
ref_clk_out_n,
iic_scl,
iic_sda,
iic_mux_scl,
iic_mux_sda,
otg_vbusoc);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [31:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [15:0] hdmi_data;
output spdif;
output i2s_mclk;
output i2s_bclk;
output i2s_lrclk;
output i2s_sdata_out;
input i2s_sdata_in;
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output dac_frame_out_p;
output dac_frame_out_n;
output [15:0] dac_data_out_p;
output [15:0] dac_data_out_n;
input adc_clk_in_p;
input adc_clk_in_n;
input adc_or_in_p;
input adc_or_in_n;
input [13:0] adc_data_in_p;
input [13:0] adc_data_in_n;
output ref_clk_out_p;
output ref_clk_out_n;
inout iic_scl;
inout iic_sda;
inout [ 1:0] iic_mux_scl;
inout [ 1:0] iic_mux_sda;
input otg_vbusoc;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 2:0] spi0_csn;
wire spi0_clk;
wire spi0_mosi;
wire spi0_miso;
wire [ 2:0] spi1_csn;
wire spi1_clk;
wire spi1_mosi;
wire spi1_miso;
wire ref_clk;
wire oddr_ref_clk;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
wire [15:0] ps_intrs;
// instantiations
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
i_oddr_ref_clk (
.S (1'b0),
.CE (1'b1),
.R (1'b0),
.C (ref_clk),
.D1 (1'b1),
.D2 (1'b0),
.Q (oddr_ref_clk));
OBUFDS i_obufds_ref_clk (
.I (oddr_ref_clk),
.O (ref_clk_out_p),
.OB (ref_clk_out_n));
ad_iobuf #(
.DATA_WIDTH(32))
i_gpio_bd (
.dio_t(gpio_t[31:0]),
.dio_i(gpio_o[31:0]),
.dio_o(gpio_i[31:0]),
.dio_p(gpio_bd));
ad_iobuf #(
.DATA_WIDTH(2))
i_iic_mux_scl (
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i(iic_mux_scl_o_s),
.dio_o(iic_mux_scl_i_s),
.dio_p(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2))
i_iic_mux_sda (
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i(iic_mux_sda_o_s),
.dio_o(iic_mux_sda_i_s),
.dio_p(iic_mux_sda));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.adc_clk_in_n (adc_clk_in_n),
.adc_clk_in_p (adc_clk_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_or_in_n (adc_or_in_n),
.adc_or_in_p (adc_or_in_p),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_data_out_n (dac_data_out_n),
.dac_data_out_p (dac_data_out_p),
.dac_frame_out_n (dac_frame_out_n),
.dac_frame_out_p (dac_frame_out_p),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_i (iic_mux_scl_i_s),
.iic_mux_scl_o (iic_mux_scl_o_s),
.iic_mux_scl_t (iic_mux_scl_t_s),
.iic_mux_sda_i (iic_mux_sda_i_s),
.iic_mux_sda_o (iic_mux_sda_o_s),
.iic_mux_sda_t (iic_mux_sda_t_s),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ref_clk (ref_clk),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif),
.spi0_clk_i (spi0_clk),
.spi0_clk_o (spi0_clk),
.spi0_csn_0_o (spi0_csn[0]),
.spi0_csn_1_o (spi0_csn[1]),
.spi0_csn_2_o (spi0_csn[2]),
.spi0_csn_i (1'b1),
.spi0_sdi_i (spi0_miso),
.spi0_sdo_i (spi0_mosi),
.spi0_sdo_o (spi0_mosi),
.spi1_clk_i (spi1_clk),
.spi1_clk_o (spi1_clk),
.spi1_csn_0_o (spi1_csn[0]),
.spi1_csn_1_o (spi1_csn[1]),
.spi1_csn_2_o (spi1_csn[2]),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b1),
.spi1_sdo_i (spi1_mosi),
.spi1_sdo_o (spi1_mosi));
endmodule
// ***************************************************************************
// ***************************************************************************