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ad_dds: Registered dds_scale so that Vivado can optimally map the dsp block

main
Adrian Costina 2015-10-09 13:43:14 +03:00
parent 88e8bef92f
commit 96d363849e
1 changed files with 13 additions and 7 deletions
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20
library/common/ad_dds.v
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@ -1,9 +1,9 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
//
// All rights reserved.
//
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
@ -21,16 +21,16 @@
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
@ -66,6 +66,8 @@ module ad_dds (
reg [15:0] dds_data_int = 'd0;
reg [15:0] dds_data = 'd0;
reg [15:0] dds_scale_0_r = 'd0;
reg [15:0] dds_scale_1_r = 'd0;
// internal signals
wire [15:0] dds_data_0_s;
@ -79,12 +81,16 @@ module ad_dds (
dds_data[14: 0] <= dds_data_int[14:0];
end
always @(posedge clk) begin
dds_scale_0_r <= dds_scale_0;
dds_scale_1_r <= dds_scale_1;
end
// dds-1
ad_dds_1 i_dds_1_0 (
.clk (clk),
.angle (dds_phase_0),
.scale (dds_scale_0),
.scale (dds_scale_0_r),
.dds_data (dds_data_0_s));
// dds-2
@ -92,7 +98,7 @@ module ad_dds (
ad_dds_1 i_dds_1_1 (
.clk (clk),
.angle (dds_phase_1),
.scale (dds_scale_1),
.scale (dds_scale_1_r),
.dds_data (dds_data_1_s));
endmodule