axi_i2s: Add missing signals to the regmap read process sensitivity list
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
parent
32dd1d1a4a
commit
96339ba96f
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@ -405,7 +405,7 @@ begin
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wr_stb => wr_stb
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wr_stb => wr_stb
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);
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);
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process(rd_addr)
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process(rd_addr, I2S_CONTROL_REG, I2S_CLK_CONTROL_REG, PERIOD_LEN_REG, rx_sample, cnt)
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begin
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begin
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case rd_addr is
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case rd_addr is
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when 1 => rd_data <= I2S_CONTROL_REG and x"00000003";
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when 1 => rd_data <= I2S_CONTROL_REG and x"00000003";
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