fmcomms2: Updated kc705 project to vivado 2014.2.
- Updated interrupt system to the latest implementation - Fixed constraints - Used ad_iobufmain
parent
db18ed4af2
commit
962df53946
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@ -60,8 +60,5 @@ set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVCMOS25} [get_ports spi_miso
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# clocks
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# clocks
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create_clock -name rx_clk -period 5 [get_ports rx_clk_in_p]
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create_clock -name rx_clk -period 4 [get_ports rx_clk_in_p]
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create_clock -name ad9361_clk -period 5 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
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create_clock -name ad9361_clk -period 4 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
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set_clock_groups -asynchronous -group {ad9361_clk}
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@ -8,6 +8,7 @@ adi_project_create fmcomms2_kc705
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adi_project_files fmcomms2_kc705 [list \
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adi_project_files fmcomms2_kc705 [list \
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"system_top.v" \
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"system_top.v" \
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"system_constr.xdc"\
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"system_constr.xdc"\
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"$ad_hdl_dir/library/common/ad_iobuf.v" \
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"$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc" ]
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"$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc" ]
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adi_project_run fmcomms2_kc705
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adi_project_run fmcomms2_kc705
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@ -1,9 +1,9 @@
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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// Copyright 2011(c) Analog Devices, Inc.
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//
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//
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// - Redistributions of source code must retain the above copyright
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@ -21,16 +21,16 @@
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// patent holders to use this software.
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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// on or directly connected to an Analog Devices Inc. component.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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@ -96,21 +96,21 @@ module system_top (
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hdmi_data,
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hdmi_data,
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spdif,
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spdif,
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rx_clk_in_p,
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rx_clk_in_p,
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rx_clk_in_n,
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rx_clk_in_n,
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rx_frame_in_p,
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rx_frame_in_p,
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rx_frame_in_n,
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rx_frame_in_n,
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rx_data_in_p,
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rx_data_in_p,
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rx_data_in_n,
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rx_data_in_n,
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tx_clk_out_p,
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tx_clk_out_p,
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tx_clk_out_n,
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tx_clk_out_n,
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tx_frame_out_p,
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tx_frame_out_p,
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tx_frame_out_n,
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tx_frame_out_n,
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tx_data_out_p,
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tx_data_out_p,
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tx_data_out_n,
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tx_data_out_n,
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gpio_txnrx,
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gpio_txnrx,
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gpio_enable,
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gpio_enable,
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gpio_resetb,
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gpio_resetb,
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@ -122,7 +122,7 @@ module system_top (
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spi_csn,
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spi_csn,
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spi_clk,
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spi_clk,
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spi_mosi,
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spi_mosi,
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spi_miso
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spi_miso
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);
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);
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input sys_rst;
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input sys_rst;
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@ -180,14 +180,14 @@ module system_top (
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output [15:0] hdmi_data;
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output [15:0] hdmi_data;
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output spdif;
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output spdif;
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input rx_clk_in_p;
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input rx_clk_in_p;
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input rx_clk_in_n;
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input rx_clk_in_n;
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input rx_frame_in_p;
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input rx_frame_in_p;
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input rx_frame_in_n;
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input rx_frame_in_n;
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input [ 5:0] rx_data_in_p;
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input [ 5:0] rx_data_in_p;
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input [ 5:0] rx_data_in_n;
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input [ 5:0] rx_data_in_n;
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output tx_clk_out_p;
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output tx_clk_out_p;
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output tx_clk_out_n;
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output tx_clk_out_n;
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output tx_frame_out_p;
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output tx_frame_out_p;
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@ -202,67 +202,31 @@ module system_top (
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inout gpio_en_agc;
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inout gpio_en_agc;
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inout [ 3:0] gpio_ctl;
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inout [ 3:0] gpio_ctl;
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inout [ 7:0] gpio_status;
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inout [ 7:0] gpio_status;
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output spi_csn;
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output spi_csn;
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output spi_clk;
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output spi_clk;
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output spi_mosi;
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output spi_mosi;
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input spi_miso;
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input spi_miso;
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// internal signals
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// internal signals
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wire [16:0] gpio_i;
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wire [16:0] gpio_i;
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wire [16:0] gpio_o;
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wire [16:0] gpio_o;
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wire [16:0] gpio_t;
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wire [16:0] gpio_t;
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wire [31:0] mb_intrs;
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// instantiations
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// instantiations
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IOBUF i_iobuf_gpio_txnrx (
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.I (gpio_o[16]),
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.O (gpio_i[16]),
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.T (gpio_t[16]),
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.IO (gpio_txnrx));
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IOBUF i_iobuf_gpio_enable (
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ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
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.I (gpio_o[15]),
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.dt (gpio_t[16:0]),
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.O (gpio_i[15]),
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.di (gpio_o[16:0]),
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.T (gpio_t[15]),
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.do (gpio_i[16:0]),
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.IO (gpio_enable));
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.dio({ gpio_txnrx,
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gpio_enable,
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IOBUF i_iobuf_gpio_resetb (
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gpio_resetb,
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.I (gpio_o[14]),
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gpio_sync,
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.O (gpio_i[14]),
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gpio_en_agc,
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.T (gpio_t[14]),
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gpio_ctl,
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.IO (gpio_resetb));
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gpio_status}));
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IOBUF i_iobuf_gpio_sync (
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.I (gpio_o[13]),
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.O (gpio_i[13]),
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.T (gpio_t[13]),
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.IO (gpio_sync));
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IOBUF i_iobuf_gpio_en_agc (
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.I (gpio_o[12]),
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.O (gpio_i[12]),
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.T (gpio_t[12]),
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.IO (gpio_en_agc));
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genvar n;
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generate
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for (n = 0; n <= 3; n = n + 1) begin: g_iobuf_gpio_ctl
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IOBUF i_iobuf_gpio_ctl (
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.I (gpio_o[8+n]),
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.O (gpio_i[8+n]),
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.T (gpio_t[8+n]),
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.IO (gpio_ctl[n]));
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end
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for (n = 0; n <= 7; n = n + 1) begin: g_iobuf_gpio_status
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IOBUF i_iobuf_gpio_status (
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.I (gpio_o[0+n]),
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.O (gpio_i[0+n]),
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.T (gpio_t[0+n]),
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.IO (gpio_status[n]));
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end
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endgenerate
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system_wrapper i_system_wrapper (
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system_wrapper i_system_wrapper (
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.ddr3_1_n (ddr3_1_n),
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.ddr3_1_n (ddr3_1_n),
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@ -297,6 +261,32 @@ module system_top (
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.iic_main_scl_io (iic_scl),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.iic_main_sda_io (iic_sda),
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.iic_rstn (iic_rstn),
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.iic_rstn (iic_rstn),
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.mb_intr_10 (mb_intrs[10]),
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.mb_intr_11 (mb_intrs[11]),
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.mb_intr_12 (mb_intrs[12]),
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.mb_intr_13 (mb_intrs[13]),
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.mb_intr_14 (mb_intrs[14]),
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.mb_intr_15 (mb_intrs[15]),
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.mb_intr_16 (mb_intrs[16]),
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.mb_intr_17 (mb_intrs[17]),
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.mb_intr_18 (mb_intrs[18]),
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.mb_intr_19 (mb_intrs[19]),
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.mb_intr_20 (mb_intrs[20]),
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.mb_intr_21 (mb_intrs[21]),
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.mb_intr_22 (mb_intrs[22]),
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.mb_intr_23 (mb_intrs[23]),
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.mb_intr_24 (mb_intrs[24]),
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.mb_intr_25 (mb_intrs[25]),
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.mb_intr_26 (mb_intrs[26]),
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.mb_intr_27 (mb_intrs[27]),
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.mb_intr_28 (mb_intrs[28]),
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.mb_intr_29 (mb_intrs[29]),
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.mb_intr_30 (mb_intrs[30]),
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.mb_intr_31 (mb_intrs[31]),
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.fmcomms2_spi_irq(mb_intrs[10]),
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.fmcomms2_gpio_irq(mb_intrs[11]),
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.ad9361_adc_dma_irq (mb_intrs[12]),
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.ad9361_dac_dma_irq (mb_intrs[13]),
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.mdio_mdc (mdio_mdc),
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.mdio_mdc (mdio_mdc),
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.mdio_mdio_io (mdio_mdio_io),
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.mdio_mdio_io (mdio_mdio_io),
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.mii_col (mii_col),
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.mii_col (mii_col),
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@ -314,7 +304,7 @@ module system_top (
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.sys_clk_p (sys_clk_p),
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.sys_clk_p (sys_clk_p),
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.sys_rst (sys_rst),
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.sys_rst (sys_rst),
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.spi_csn_i (1'b1),
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.spi_csn_i (1'b1),
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.spi_csn_o (spi_csn),
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.spi_csn_o (spi_csn),
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.spi_miso_i (spi_miso),
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.spi_miso_i (spi_miso),
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.spi_mosi_i (1'b0),
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.spi_mosi_i (1'b0),
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.spi_mosi_o (spi_mosi),
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.spi_mosi_o (spi_mosi),
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.rx_data_in_n (rx_data_in_n),
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.rx_data_in_n (rx_data_in_n),
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.rx_data_in_p (rx_data_in_p),
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.rx_data_in_p (rx_data_in_p),
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.rx_frame_in_n (rx_frame_in_n),
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.rx_frame_in_n (rx_frame_in_n),
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.rx_frame_in_p (rx_frame_in_p),
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.rx_frame_in_p (rx_frame_in_p),
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.tx_clk_out_n (tx_clk_out_n),
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.tx_clk_out_n (tx_clk_out_n),
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.tx_clk_out_p (tx_clk_out_p),
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.tx_clk_out_p (tx_clk_out_p),
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.tx_data_out_n (tx_data_out_n),
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.tx_data_out_n (tx_data_out_n),
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.tx_data_out_p (tx_data_out_p),
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.tx_data_out_p (tx_data_out_p),
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.tx_frame_out_n (tx_frame_out_n),
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.tx_frame_out_n (tx_frame_out_n),
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.tx_frame_out_p (tx_frame_out_p),
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.tx_frame_out_p (tx_frame_out_p),
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.uart_sin (uart_sin),
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.uart_sin (uart_sin),
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.uart_sout (uart_sout),
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.uart_sout (uart_sout));
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.unc_int0 (1'b0),
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.unc_int3 (1'b0));
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endmodule
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endmodule
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