zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fmcomms2: Modified design to work with 4 channel util_adc_pack

main
Adrian Costina 2014-08-29 13:53:59 +03:00
parent cf660c126d
commit 95c143412d
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
projects/fmcomms2/common/fmcomms2_bd.tcl
View File

@ -49,6 +49,7 @@
# channel packing for the ADC
set util_adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 util_adc_pack]
set_property -dict [list CONFIG.CHANNELS {4}] $util_adc_pack
set util_dac_unpack [create_bd_cell -type ip -vlnv analog.com:user:util_dac_unpack:1.0 util_dac_unpack]
@ -72,7 +73,7 @@ if {$sys_zynq == 1} {
set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9361_adc_dma
if {$sys_zynq == 1} {
set axi_ad9361_adc_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9361_adc_dma_interconnect]