diff --git a/projects/pzsdr1/ccbox_lvds/Makefile b/projects/pzsdr1/ccbox_lvds/Makefile new file mode 100644 index 000000000..20dd931d1 --- /dev/null +++ b/projects/pzsdr1/ccbox_lvds/Makefile @@ -0,0 +1,82 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += system_top.v +M_DEPS += system_project.tcl +M_DEPS += system_constr.xdc +M_DEPS += system_bd.tcl +M_DEPS += ../common/ccbrk_bd.tcl +M_DEPS += ../../scripts/adi_project.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_board.tcl +M_DEPS += ../../fmcomms2/common/fmcomms2_bd.tcl +M_DEPS += ../../common/xilinx/sys_wfifo.tcl +M_DEPS += ../../common/pzsdr1/pzsdr1_system_constr.xdc +M_DEPS += ../../common/pzsdr1/pzsdr1_system_bd.tcl +M_DEPS += ../../common/pzsdr1/pzsdr1_lvds_system_constr.xdc +M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr +M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr +M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr +M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr +M_DEPS += ../../../library/util_upack/util_upack.xpr +M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.runs +M_FLIST += *.srcs +M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil +M_FLIST += *.ip_user_files + + + +.PHONY: all lib clean clean-all +all: lib ccbrk_pzsdr1.sdk/system_top.hdf + + +clean: + rm -rf $(M_FLIST) + + +clean-all:clean + make -C ../../../library/axi_ad9361 clean + make -C ../../../library/axi_dmac clean + make -C ../../../library/axi_gpreg clean + make -C ../../../library/util_cpack clean + make -C ../../../library/util_tdd_sync clean + make -C ../../../library/util_upack clean + make -C ../../../library/util_wfifo clean + + +ccbrk_pzsdr1.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> ccbrk_pzsdr1_vivado.log 2>&1 + + +lib: + make -C ../../../library/axi_ad9361 + make -C ../../../library/axi_dmac + make -C ../../../library/axi_gpreg + make -C ../../../library/util_cpack + make -C ../../../library/util_tdd_sync + make -C ../../../library/util_upack + make -C ../../../library/util_wfifo + +#################################################################################### +#################################################################################### diff --git a/projects/pzsdr1/ccbox_lvds/system_bd.tcl b/projects/pzsdr1/ccbox_lvds/system_bd.tcl new file mode 100644 index 000000000..aa8108693 --- /dev/null +++ b/projects/pzsdr1/ccbox_lvds/system_bd.tcl @@ -0,0 +1,4 @@ + +source $ad_hdl_dir/projects/common/pzsdr1/pzsdr1_system_bd.tcl +source ../common/ccbrk_bd.tcl + diff --git a/projects/pzsdr1/ccbox_lvds/system_constr.xdc b/projects/pzsdr1/ccbox_lvds/system_constr.xdc new file mode 100644 index 000000000..e54ad79c8 --- /dev/null +++ b/projects/pzsdr1/ccbox_lvds/system_constr.xdc @@ -0,0 +1,97 @@ + +## constraints +## loopback +## p6 + +set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVCMOS25} [get_ports gp_out[0]] ; ## JX4.20 IO_L2P_T0_34 +set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS25} [get_ports gp_in[0]] ; ## JX4.19 IO_L1P_T0_34 +set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS25} [get_ports gp_out[1]] ; ## JX4.22 IO_L2N_T0_34 +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS25} [get_ports gp_in[1]] ; ## JX4.21 IO_L1N_T0_34 +set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS25} [get_ports gp_out[2]] ; ## JX4.26 IO_L4P_T0_34 +set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS25} [get_ports gp_in[2]] ; ## JX4.25 IO_L3P_T0_DQS_PUDC_B_34 +set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS25} [get_ports gp_out[3]] ; ## JX4.28 IO_L4N_T0_34 +set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS25} [get_ports gp_in[3]] ; ## JX4.27 IO_L3N_T0_DQS_34 +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS25} [get_ports gp_out[4]] ; ## JX4.32 IO_L6P_T0_34 +set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS25} [get_ports gp_in[4]] ; ## JX4.31 IO_L5P_T0_34 +set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS25} [get_ports gp_out[5]] ; ## JX4.34 IO_L6N_T0_VREF_34 +set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS25} [get_ports gp_in[5]] ; ## JX4.33 IO_L5N_T0_34 +set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVCMOS25} [get_ports gp_out[6]] ; ## JX4.36 IO_L8P_T1_34 +set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS25} [get_ports gp_in[6]] ; ## JX4.35 IO_L7P_T1_34 +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS25} [get_ports gp_out[7]] ; ## JX4.46 IO_L12P_T1_MRCC_34 +set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS25} [get_ports gp_in[7]] ; ## JX4.45 IO_L11P_T1_SRCC_34 +set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS25} [get_ports gp_out[8]] ; ## JX4.48 IO_L12N_T1_MRCC_34 +set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS25} [get_ports gp_in[8]] ; ## JX4.47 IO_L11N_T1_SRCC_34 + +## p7 + +set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports gp_out[9]] ; ## JX4.52 IO_L14P_T2_SRCC_34 +set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS25} [get_ports gp_in[9]] ; ## JX4.51 IO_L13P_T2_MRCC_34 +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports gp_out[10]] ; ## JX4.54 IO_L14N_T2_SRCC_34 +set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS25} [get_ports gp_in[10]] ; ## JX4.53 IO_L13N_T2_MRCC_34 +set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS25} [get_ports gp_out[11]] ; ## JX4.58 IO_L16P_T2_34 +set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS25} [get_ports gp_in[11]] ; ## JX4.57 IO_L15P_T2_DQS_34 +set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS25} [get_ports gp_out[12]] ; ## JX4.60 IO_L16N_T2_34 +set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS25} [get_ports gp_in[12]] ; ## JX4.59 IO_L15N_T2_DQS_34 +set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports gp_out[13]] ; ## JX4.74 IO_L20P_T3_34 +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS25} [get_ports gp_in[13]] ; ## JX4.73 IO_L19P_T3_34 +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS25} [get_ports gp_out[14]] ; ## JX4.76 IO_L20N_T3_34 +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS25} [get_ports gp_in[14]] ; ## JX4.75 IO_L19N_T3_VREF_34 +set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS25} [get_ports gp_out[15]] ; ## JX4.78 IO_L22P_T3_34 +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS25} [get_ports gp_in[15]] ; ## JX4.77 IO_L21P_T3_DQS_34 +set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports gp_out[16]] ; ## JX4.80 IO_L22N_T3_34 +set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS25} [get_ports gp_in[16]] ; ## JX4.79 IO_L21N_T3_DQS_34 + +## p2 + +set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS25} [get_ports gp_out[17]] ; ## JX2.36 IO_L12P_T1_MRCC_13 +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS25} [get_ports gp_in[17]] ; ## JX2.35 IO_L11P_T1_SRCC_13 +set_property -dict {PACKAGE_PIN U10 IOSTANDARD LVCMOS25} [get_ports gp_out[18]] ; ## JX2.38 IO_L12N_T1_MRCC_13 +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS25} [get_ports gp_in[18]] ; ## JX2.37 IO_L11N_T1_SRCC_13 +set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS25} [get_ports gp_out[19]] ; ## JX2.42 IO_L14P_T2_SRCC_13 +set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS25} [get_ports gp_in[19]] ; ## JX2.41 IO_L13P_T2_MRCC_13 +set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS25} [get_ports gp_out[20]] ; ## JX2.44 IO_L14N_T2_SRCC_13 +set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS25} [get_ports gp_in[20]] ; ## JX2.43 IO_L13N_T2_MRCC_13 +set_property -dict {PACKAGE_PIN W10 IOSTANDARD LVCMOS25} [get_ports gp_out[21]] ; ## JX2.48 IO_L16P_T2_13 +set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS25} [get_ports gp_in[21]] ; ## JX2.47 IO_L15P_T2_DQS_13 +set_property -dict {PACKAGE_PIN W9 IOSTANDARD LVCMOS25} [get_ports gp_out[22]] ; ## JX2.50 IO_L16N_T2_13 +set_property -dict {PACKAGE_PIN W8 IOSTANDARD LVCMOS25} [get_ports gp_in[22]] ; ## JX2.49 IO_L15N_T2_DQS_13 +set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVCMOS25} [get_ports gp_out[23]] ; ## JX2.54 IO_L18P_T2_13 +set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS25} [get_ports gp_in[23]] ; ## JX2.53 IO_L17P_T2_13 +set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS25} [get_ports gp_out[24]] ; ## JX2.56 IO_L18N_T2_13 +set_property -dict {PACKAGE_PIN U8 IOSTANDARD LVCMOS25} [get_ports gp_in[24]] ; ## JX2.55 IO_L17N_T2_13 +set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS25} [get_ports gp_out[25]] ; ## JX2.62 IO_L20P_T3_13 +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS25} [get_ports gp_in[25]] ; ## JX2.61 IO_L19P_T3_13 +set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS25} [get_ports gp_out[26]] ; ## JX2.64 IO_L20N_T3_13 +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS25} [get_ports gp_in[26]] ; ## JX2.63 IO_L19N_T3_VREF_13 + +## vcc + +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS25} [get_ports gp_in_open[0]] ; ## JX2.18 IO_L6N_T0_VREF_13 +set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS25} [get_ports gp_in_open[1]] ; ## JX4.68 IO_L18P_T2_34 +set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS25} [get_ports gp_in_open[2]] ; ## JX4.70 IO_L18N_T2_34 +set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS25} [get_ports gp_in_open[3]] ; ## JX2.67 IO_L21P_T3_DQS_13 +set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS25} [get_ports gp_in_open[4]] ; ## JX2.69 IO_L21N_T3_DQS_13 + +## MIO loopbacks (fixed-io) +## the following are connected to AD9361 GPIO + +## JX4.86 A23 PS_MIO12_500_JX4 <==> JX4.2 NA AD9361_GPO1 +## JX4.88 B26 PS_MIO11_500_JX4 <==> JX4.1 NA AD9361_GPO0 +## JX4.91 B25 PS_MIO13_500_JX4 <==> JX4.3 NA AD9361_GPO2 +## JX4.93 D23 PS_MIO14_500_JX4 <==> JX4.4 NA AD9361_GPO3 + +## the following are mio-to-mio loopback (excluding Push-Buttons to LED) + +## JX4.92 E17 PS_MIO46_501_JX4 <==> JX4.94 B19 PS_MIO47_501_JX4 + +## the following are mio-to-pl loopback + +## JX4.100 B20 PS_MIO51_501_JX4 <==> JX4.67 A9 IO_L17P_T2_34 +## JX4.85 C24 PS_MIO15_500_JX4 <==> JX4.37 E5 IO_L7N_T1_34 +## JX4.87 A25 PS_MIO10_500_JX4 <==> JX4.42 E6 IO_L10P_T1_34 + +set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS25} [get_ports gp_in_mio[0]] ; ## JX4.67 IO_L17P_T2_34 +set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS25} [get_ports gp_in_mio[1]] ; ## JX4.37 IO_L7N_T1_34 +set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS25} [get_ports gp_in_mio[2]] ; ## JX4.42 IO_L10P_T1_34 + + diff --git a/projects/pzsdr1/ccbox_lvds/system_project.tcl b/projects/pzsdr1/ccbox_lvds/system_project.tcl new file mode 100644 index 000000000..21967b370 --- /dev/null +++ b/projects/pzsdr1/ccbox_lvds/system_project.tcl @@ -0,0 +1,17 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project_create ccbrk_pzsdr1 +adi_project_files ccbrk_pzsdr1 [list \ + "system_top.v" \ + "system_constr.xdc"\ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/pzsdr1/pzsdr1_system_constr.xdc" \ + "$ad_hdl_dir/projects/common/pzsdr1/pzsdr1_lvds_system_constr.xdc" ] + +set_property is_enabled false [get_files *axi_gpreg_constr.xdc] +adi_project_run ccbrk_pzsdr1 + + diff --git a/projects/pzsdr1/ccbox_lvds/system_top.v b/projects/pzsdr1/ccbox_lvds/system_top.v new file mode 100644 index 000000000..643b39163 --- /dev/null +++ b/projects/pzsdr1/ccbox_lvds/system_top.v @@ -0,0 +1,287 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + ddr_addr, + ddr_ba, + ddr_cas_n, + ddr_ck_n, + ddr_ck_p, + ddr_cke, + ddr_cs_n, + ddr_dm, + ddr_dq, + ddr_dqs_n, + ddr_dqs_p, + ddr_odt, + ddr_ras_n, + ddr_reset_n, + ddr_we_n, + + fixed_io_ddr_vrn, + fixed_io_ddr_vrp, + fixed_io_mio, + fixed_io_ps_clk, + fixed_io_ps_porb, + fixed_io_ps_srstb, + + iic_scl, + iic_sda, + + gpio_bd, + + rx_clk_in_p, + rx_clk_in_n, + rx_frame_in_p, + rx_frame_in_n, + rx_data_in_p, + rx_data_in_n, + tx_clk_out_p, + tx_clk_out_n, + tx_frame_out_p, + tx_frame_out_n, + tx_data_out_p, + tx_data_out_n, + + enable, + txnrx, + clk_out, + + gpio_clksel, + gpio_resetb, + gpio_sync, + gpio_en_agc, + gpio_ctl, + gpio_status, + + spi_csn, + spi_clk, + spi_mosi, + spi_miso, + + gp_out, + gp_in, + gp_in_mio, + gp_in_open); + + + inout [14:0] ddr_addr; + inout [ 2:0] ddr_ba; + inout ddr_cas_n; + inout ddr_ck_n; + inout ddr_ck_p; + inout ddr_cke; + inout ddr_cs_n; + inout [ 3:0] ddr_dm; + inout [31:0] ddr_dq; + inout [ 3:0] ddr_dqs_n; + inout [ 3:0] ddr_dqs_p; + inout ddr_odt; + inout ddr_ras_n; + inout ddr_reset_n; + inout ddr_we_n; + + inout fixed_io_ddr_vrn; + inout fixed_io_ddr_vrp; + inout [53:0] fixed_io_mio; + inout fixed_io_ps_clk; + inout fixed_io_ps_porb; + inout fixed_io_ps_srstb; + + inout iic_scl; + inout iic_sda; + + inout [ 3:0] gpio_bd; + + input rx_clk_in_p; + input rx_clk_in_n; + input rx_frame_in_p; + input rx_frame_in_n; + input [ 5:0] rx_data_in_p; + input [ 5:0] rx_data_in_n; + output tx_clk_out_p; + output tx_clk_out_n; + output tx_frame_out_p; + output tx_frame_out_n; + output [ 5:0] tx_data_out_p; + output [ 5:0] tx_data_out_n; + + output enable; + output txnrx; + input clk_out; + + inout gpio_clksel; + inout gpio_resetb; + inout gpio_sync; + inout gpio_en_agc; + inout [ 3:0] gpio_ctl; + inout [ 7:0] gpio_status; + + output spi_csn; + output spi_clk; + output spi_mosi; + input spi_miso; + + output [26:0] gp_out; + input [26:0] gp_in; + input [ 2:0] gp_in_mio; + input [ 4:0] gp_in_open; + + // internal signals + + wire [63:0] gp_out_s; + wire [63:0] gp_in_s; + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + // assignments + + assign gp_out[26:0] = gp_out_s[26:0]; + assign gp_in_s[34:30] = gp_in_open; + assign gp_in_s[29:27] = gp_in_mio; + assign gp_in_s[26: 0] = gp_in; + + // instantiations + + ad_iobuf #(.DATA_WIDTH(16)) i_iobuf ( + .dio_t ({gpio_t[51], gpio_t[46:32]}), + .dio_i ({gpio_o[51], gpio_o[46:32]}), + .dio_o ({gpio_i[51], gpio_i[46:32]}), + .dio_p ({ gpio_clksel, // 51:51 + gpio_resetb, // 46:46 + gpio_sync, // 45:45 + gpio_en_agc, // 44:44 + gpio_ctl, // 43:40 + gpio_status})); // 39:32 + + ad_iobuf #(.DATA_WIDTH(4)) i_iobuf_bd ( + .dio_t (gpio_t[3:0]), + .dio_i (gpio_o[3:0]), + .dio_o (gpio_i[3:0]), + .dio_p (gpio_bd)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .enable (enable), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gp_in_0 (gp_in_s[31:0]), + .gp_in_1 (gp_in_s[63:32]), + .gp_out_0 (gp_out_s[31:0]), + .gp_out_1 (gp_out_s[63:32]), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .otg_vbusoc (1'b0), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_10 (1'b0), + .ps_intr_11 (1'b0), + .ps_intr_15 (1'b0), + .rx_clk_in_n (rx_clk_in_n), + .rx_clk_in_p (rx_clk_in_p), + .rx_data_in_n (rx_data_in_n), + .rx_data_in_p (rx_data_in_p), + .rx_frame_in_n (rx_frame_in_n), + .rx_frame_in_p (rx_frame_in_p), + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_clk), + .spi0_csn_0_o (spi_csn), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_mosi), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o (), + .tdd_sync_i (1'b0), + .tdd_sync_o (), + .tdd_sync_t (), + .tx_clk_out_n (tx_clk_out_n), + .tx_clk_out_p (tx_clk_out_p), + .tx_data_out_n (tx_data_out_n), + .tx_data_out_p (tx_data_out_p), + .tx_frame_out_n (tx_frame_out_n), + .tx_frame_out_p (tx_frame_out_p), + .txnrx (txnrx), + .up_enable (gpio_o[47]), + .up_txnrx (gpio_o[48])); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/pzsdr1/common/ccbox_bd.tcl b/projects/pzsdr1/common/ccbox_bd.tcl new file mode 100644 index 000000000..204545923 --- /dev/null +++ b/projects/pzsdr1/common/ccbox_bd.tcl @@ -0,0 +1,29 @@ + +# lbfmc + +ad_connect sys_ps7/ENET1_GMII_RX_CLK GND +ad_connect sys_ps7/ENET1_GMII_TX_CLK GND + +# un-used io + +set axi_gpreg [create_bd_cell -type ip -vlnv analog.com:user:axi_gpreg:1.0 axi_gpreg] +set_property -dict [list CONFIG.NUM_OF_CLK_MONS {0}] $axi_gpreg +set_property -dict [list CONFIG.NUM_OF_IO {2}] $axi_gpreg + +ad_cpu_interconnect 0x41200000 axi_gpreg + +create_bd_port -dir I -from 31 -to 0 gp_in_0 +create_bd_port -dir I -from 31 -to 0 gp_in_1 +create_bd_port -dir O -from 31 -to 0 gp_out_0 +create_bd_port -dir O -from 31 -to 0 gp_out_1 + +ad_connect gp_in_0 axi_gpreg/up_gp_in_0 +ad_connect gp_in_1 axi_gpreg/up_gp_in_1 +ad_connect gp_out_0 axi_gpreg/up_gp_out_0 +ad_connect gp_out_1 axi_gpreg/up_gp_out_1 + +## temporary (remove ila indirectly) + +delete_bd_objs [get_bd_cells ila_adc] +delete_bd_objs [get_bd_nets axi_ad9361_tdd_dbg] [get_bd_cells ila_tdd] +