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daq1/cpld: Update CPLD 

Change to control line fpga_to_cpld to cpld_to_fpga, this is not a functional change.
main
Istvan Csomortani 2016-03-04 18:48:52 +02:00
parent 583ef82fd0
commit 9439862301
1 changed files with 10 additions and 10 deletions
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20
projects/daq1/cpld/daq1_cpld.v
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@ -136,7 +136,7 @@ module daq1_cpld (
reg [ 7:0] dac_status = 8'b0; reg [ 7:0] dac_status = 8'b0;
reg [ 7:0] clk_status = 8'b0; reg [ 7:0] clk_status = 8'b0;
reg fpga_to_cpld = 1'b1; reg cpld_to_fpga = 1'b0;
reg [ 7:0] cpld_rdata = 8'b0; reg [ 7:0] cpld_rdata = 8'b0;
reg cpld_rdata_bit = 1'b0; reg cpld_rdata_bit = 1'b0;
reg [ 2:0] cpld_rdata_index = 3'h0; reg [ 2:0] cpld_rdata_index = 3'h0;
@ -172,25 +172,25 @@ module daq1_cpld (
// SPI control and data // SPI control and data
assign sdio = fpga_to_cpld ? fmc_spi_sdio : 1'bZ; assign sdio = cpld_to_fpga ? 1'bZ : fmc_spi_sdio;
assign fmc_spi_sdio = fpga_to_cpld ? 1'bZ : cpld_rdata_s; assign fmc_spi_sdio = cpld_to_fpga ? cpld_rdata_s : 1'bZ ;
assign cpld_rdata_s = cpld_spicsn ? sdio : cpld_rdata_bit; assign cpld_rdata_s = cpld_spicsn ? sdio : cpld_rdata_bit;
assign rdnwr = ~fmc_cpld_addr[7]; assign rdnwr = fmc_cpld_addr[7];
assign sclk = (~(fmc_spi_csn | fmc_spi_csn_enb)) ? fmc_spi_sclk : 1'b0; assign sclk = (~(fmc_spi_csn | fmc_spi_csn_enb)) ? fmc_spi_sclk : 1'b0;
always @(negedge fmc_spi_sclk or posedge fmc_spi_csn) begin always @(negedge fmc_spi_sclk or posedge fmc_spi_csn) begin
if (fmc_spi_csn == 1'b1) begin if (fmc_spi_csn == 1'b1) begin
fmc_spi_counter <= 6'h0; fmc_spi_counter <= 6'h0;
fpga_to_cpld <= 1'b1; cpld_to_fpga <= 1'b0;
fmc_spi_csn_enb <= 1'b1; fmc_spi_csn_enb <= 1'b1;
end else begin end else begin
fmc_spi_counter <= fmc_spi_counter + 1; fmc_spi_counter <= fmc_spi_counter + 1;
fmc_spi_csn_enb <= (fmc_spi_counter < 7) ? 1'b1 : 1'b0; fmc_spi_csn_enb <= (fmc_spi_counter < 7) ? 1'b1 : 1'b0;
if (adc_spicsn & clk_spicsn) begin if (adc_spicsn & clk_spicsn) begin
fpga_to_cpld <= (fmc_spi_counter >= 15) ? rdnwr : 1'b1; cpld_to_fpga <= (fmc_spi_counter >= 15) ? rdnwr : 1'b0;
end else begin end else begin
fpga_to_cpld <= (fmc_spi_counter >= 23) ? rdnwr : 1'b1; cpld_to_fpga <= (fmc_spi_counter >= 23) ? rdnwr : 1'b0;
end end
end end
end end
@ -225,7 +225,7 @@ module daq1_cpld (
cpld_rdata_bit <= 1'b0; cpld_rdata_bit <= 1'b0;
cpld_rdata_index <= 3'h7; cpld_rdata_index <= 3'h7;
end else begin end else begin
if (fpga_to_cpld == 1'b0) begin if (cpld_to_fpga == 1'b1) begin
cpld_rdata_bit <= cpld_rdata[cpld_rdata_index]; cpld_rdata_bit <= cpld_rdata[cpld_rdata_index];
cpld_rdata_index <= cpld_rdata_index - 1; cpld_rdata_index <= cpld_rdata_index - 1;
end end
@ -234,8 +234,8 @@ module daq1_cpld (
// Internal register write access // Internal register write access
always @(fpga_to_cpld, cpld_spicsn, fmc_spi_counter) begin always @(cpld_to_fpga, cpld_spicsn, fmc_spi_counter) begin
if ((fpga_to_cpld == 1'b1) && if ((cpld_to_fpga == 1'b0) &&
(cpld_spicsn == 1'b0) && (cpld_spicsn == 1'b0) &&
(fmc_spi_counter == 8'h18)) begin (fmc_spi_counter == 8'h18)) begin
case (fmc_cpld_addr[6:0]) case (fmc_cpld_addr[6:0])