zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

axi_ad9234: Remove deprecated IP

main
Istvan Csomortani 2017-06-26 15:46:12 +01:00
parent 6bcb327d5f
commit 9363ee0316
7 changed files with 0 additions and 910 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

58
library/axi_ad9234/Makefile
View File

@ -1,58 +0,0 @@
####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS += ../common/ad_pnmon.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += axi_ad9234.v
M_DEPS += axi_ad9234_channel.v
M_DEPS += axi_ad9234_constr.xdc
M_DEPS += axi_ad9234_if.v
M_DEPS += axi_ad9234_ip.tcl
M_DEPS += axi_ad9234_pnmon.v
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.ip_user_files
M_FLIST += *.srcs
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
.PHONY: all clean clean-all
all: axi_ad9234.xpr
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
axi_ad9234.xpr: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_VIVADO) axi_ad9234_ip.tcl >> axi_ad9234_ip.log 2>&1
####################################################################################
####################################################################################

288
library/axi_ad9234/axi_ad9234.v
View File

@ -1,288 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9234 #(
parameter ID = 0,
parameter DEVICE_TYPE = 0,
parameter IO_DELAY_GROUP = "adc_if_delay_group") (
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk,
input [127:0] rx_data,
// dma interface
output adc_clk,
output adc_enable_0,
output adc_valid_0,
output [63:0] adc_data_0,
output adc_enable_1,
output adc_valid_1,
output [63:0] adc_data_1,
input adc_dovf,
input adc_dunf,
// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready,
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot);
// internal registers
reg up_status_pn_err = 'd0;
reg up_status_pn_oos = 'd0;
reg up_status_or = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal clocks & resets
wire adc_rst;
wire up_rstn;
wire up_clk;
// internal signals
wire [63:0] adc_data_a_s;
wire [63:0] adc_data_b_s;
wire adc_or_a_s;
wire adc_or_b_s;
wire adc_status_s;
wire [ 1:0] up_adc_pn_err_s;
wire [ 1:0] up_adc_pn_oos_s;
wire [ 1:0] up_adc_or_s;
wire [31:0] up_rdata_s[0:2];
wire up_rack_s[0:2];
wire up_wack_s[0:2];
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// defaults
assign adc_valid_0 = 1'b1;
assign adc_valid_1 = 1'b1;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_status_pn_err <= 'd0;
up_status_pn_oos <= 'd0;
up_status_or <= 'd0;
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_status_pn_err <= | up_adc_pn_err_s;
up_status_pn_oos <= | up_adc_pn_oos_s;
up_status_or <= | up_adc_or_s;
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2];
end
end
// main (device interface)
axi_ad9234_if i_if (
.rx_clk (rx_clk),
.rx_data (rx_data),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data_a (adc_data_a_s),
.adc_data_b (adc_data_b_s),
.adc_or_a (adc_or_a_s),
.adc_or_b (adc_or_b_s),
.adc_status (adc_status_s));
// channel
axi_ad9234_channel #(.Q_OR_I_N(0), .CHANNEL_ID(0)) i_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_a_s),
.adc_or (adc_or_a_s),
.adc_dfmt_data (adc_data_0),
.adc_enable (adc_enable_0),
.up_adc_pn_err (up_adc_pn_err_s[0]),
.up_adc_pn_oos (up_adc_pn_oos_s[0]),
.up_adc_or (up_adc_or_s[0]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
// channel
axi_ad9234_channel #(.Q_OR_I_N(1), .CHANNEL_ID(1)) i_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_b_s),
.adc_or (adc_or_b_s),
.adc_dfmt_data (adc_data_1),
.adc_enable (adc_enable_1),
.up_adc_pn_err (up_adc_pn_err_s[1]),
.up_adc_pn_oos (up_adc_pn_oos_s[1]),
.up_adc_or (up_adc_or_s[1]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
// common processor control
up_adc_common #(.ID(ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (adc_status_s),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd4),
.adc_start_code (),
.adc_sref_sync (),
.adc_sync (),
.up_adc_ce (),
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax_out (),
.up_usr_chanmax_in (8'd1),
.up_adc_gpio_in (32'd0),
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

140
library/axi_ad9234/axi_ad9234_channel.v
View File

@ -1,140 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// ADC channel-
`timescale 1ns/100ps
module axi_ad9234_channel #(
parameter Q_OR_I_N = 0,
parameter CHANNEL_ID = 0) (
// adc interface
input adc_clk,
input adc_rst,
input [63:0] adc_data,
input adc_or,
// channel interface
output [63:0] adc_dfmt_data,
output adc_enable,
output up_adc_pn_err,
output up_adc_pn_oos,
output up_adc_or,
// processor interface
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// internal signals
wire adc_pn_oos_s;
wire adc_pn_err_s;
wire [ 3:0] adc_pnseq_sel_s;
// instantiations
axi_ad9234_pnmon i_pnmon (
.adc_clk (adc_clk),
.adc_data (adc_data),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.adc_pnseq_sel (adc_pnseq_sel_s));
assign adc_dfmt_data = adc_data;
up_adc_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (),
.adc_dfmt_type (),
.adc_dfmt_enable (),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pnseq_sel (adc_pnseq_sel_s),
.adc_data_sel (),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd16),
.adc_usr_datatype_bits (8'd16),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

44
library/axi_ad9234/axi_ad9234_constr.xdc
View File

@ -1,44 +0,0 @@
set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
set ad9234_clk [get_clocks -of_objects [get_ports rx_clk]]
set_property ASYNC_REG TRUE \
[get_cells -hier *toggle_m1_reg*] \
[get_cells -hier *toggle_m2_reg*] \
[get_cells -hier *state_m1_reg*] \
[get_cells -hier *state_m2_reg*]
set_false_path \
-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_false_path \
-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
set_max_delay -datapath_only \
-from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \
[get_property PERIOD $ad9234_clk]
set_false_path \
-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_false_path \
-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
set_max_delay -datapath_only \
-from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \
[get_property PERIOD $up_clk]
set_false_path \
-from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_false_path \
-from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_max_delay -datapath_only \
-from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop}] \
[get_property PERIOD $up_clk]
set_false_path \
-to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}]

110
library/axi_ad9234/axi_ad9234_if.v
View File

@ -1,110 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface
`timescale 1ns/100ps
module axi_ad9234_if (
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk,
input [127:0] rx_data,
// adc data output
output adc_clk,
input adc_rst,
output [63:0] adc_data_a,
output [63:0] adc_data_b,
output adc_or_a,
output adc_or_b,
output reg adc_status);
// internal registers
// internal signals
wire [15:0] adc_data_a_s3_s;
wire [15:0] adc_data_a_s2_s;
wire [15:0] adc_data_a_s1_s;
wire [15:0] adc_data_a_s0_s;
wire [15:0] adc_data_b_s3_s;
wire [15:0] adc_data_b_s2_s;
wire [15:0] adc_data_b_s1_s;
wire [15:0] adc_data_b_s0_s;
// adc clock is the reference clock
assign adc_clk = rx_clk;
assign adc_or_a = 1'b0;
assign adc_or_b = 1'b0;
// adc channels
assign adc_data_a = { adc_data_a_s3_s, adc_data_a_s2_s,
adc_data_a_s1_s, adc_data_a_s0_s};
assign adc_data_b = { adc_data_b_s3_s, adc_data_b_s2_s,
adc_data_b_s1_s, adc_data_b_s0_s};
// data multiplex
assign adc_data_a_s3_s = {rx_data[ 31: 24], rx_data[ 63: 56]};
assign adc_data_a_s2_s = {rx_data[ 23: 16], rx_data[ 55: 48]};
assign adc_data_a_s1_s = {rx_data[ 15: 8], rx_data[ 47: 40]};
assign adc_data_a_s0_s = {rx_data[ 7: 0], rx_data[ 39: 32]};
assign adc_data_b_s3_s = {rx_data[ 95: 88], rx_data[127:120]};
assign adc_data_b_s2_s = {rx_data[ 87: 80], rx_data[119:112]};
assign adc_data_b_s1_s = {rx_data[ 79: 72], rx_data[111:104]};
assign adc_data_b_s0_s = {rx_data[ 71: 64], rx_data[103: 96]};
// status
always @(posedge rx_clk) begin
if (adc_rst == 1'b1) begin
adc_status <= 1'b0;
end else begin
adc_status <= 1'b1;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************

28
library/axi_ad9234/axi_ad9234_ip.tcl
View File

@ -1,28 +0,0 @@
# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad9234
adi_ip_files axi_ad9234 [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/ad_pnmon.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"axi_ad9234_pnmon.v" \
"axi_ad9234_channel.v" \
"axi_ad9234_if.v" \
"axi_ad9234.v" \
"axi_ad9234_constr.xdc" ]
adi_ip_properties axi_ad9234
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
ipx::save_core [ipx::current_core]

242
library/axi_ad9234/axi_ad9234_pnmon.v
View File

@ -1,242 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// PN monitors
`timescale 1ns/100ps
module axi_ad9234_pnmon (
// adc interface
input adc_clk,
input [63:0] adc_data,
// pn out of sync and error
output adc_pn_oos,
output adc_pn_err,
// processor interface PN9 (0x0), PN23 (0x1)
input [ 3:0] adc_pnseq_sel);
// internal registers
reg [63:0] adc_pn_data_in = 'd0;
reg [63:0] adc_pn_data_pn = 'd0;
// internal signals
wire [63:0] adc_pn_data_pn_s;
// PN23 function
function [63:0] pn23;
input [63:0] din;
reg [63:0] dout;
begin
dout[63] = din[22] ^ din[17];
dout[62] = din[21] ^ din[16];
dout[61] = din[20] ^ din[15];
dout[60] = din[19] ^ din[14];
dout[59] = din[18] ^ din[13];
dout[58] = din[17] ^ din[12];
dout[57] = din[16] ^ din[11];
dout[56] = din[15] ^ din[10];
dout[55] = din[14] ^ din[ 9];
dout[54] = din[13] ^ din[ 8];
dout[53] = din[12] ^ din[ 7];
dout[52] = din[11] ^ din[ 6];
dout[51] = din[10] ^ din[ 5];
dout[50] = din[ 9] ^ din[ 4];
dout[49] = din[ 8] ^ din[ 3];
dout[48] = din[ 7] ^ din[ 2];
dout[47] = din[ 6] ^ din[ 1];
dout[46] = din[ 5] ^ din[ 0];
dout[45] = din[ 4] ^ din[22] ^ din[17];
dout[44] = din[ 3] ^ din[21] ^ din[16];
dout[43] = din[ 2] ^ din[20] ^ din[15];
dout[42] = din[ 1] ^ din[19] ^ din[14];
dout[41] = din[ 0] ^ din[18] ^ din[13];
dout[40] = din[22] ^ din[12];
dout[39] = din[21] ^ din[11];
dout[38] = din[20] ^ din[10];
dout[37] = din[19] ^ din[ 9];
dout[36] = din[18] ^ din[ 8];
dout[35] = din[17] ^ din[ 7];
dout[34] = din[16] ^ din[ 6];
dout[33] = din[15] ^ din[ 5];
dout[32] = din[14] ^ din[ 4];
dout[31] = din[13] ^ din[ 3];
dout[30] = din[12] ^ din[ 2];
dout[29] = din[11] ^ din[ 1];
dout[28] = din[10] ^ din[ 0];
dout[27] = din[ 9] ^ din[22] ^ din[17];
dout[26] = din[ 8] ^ din[21] ^ din[16];
dout[25] = din[ 7] ^ din[20] ^ din[15];
dout[24] = din[ 6] ^ din[19] ^ din[14];
dout[23] = din[ 5] ^ din[18] ^ din[13];
dout[22] = din[ 4] ^ din[17] ^ din[12];
dout[21] = din[ 3] ^ din[16] ^ din[11];
dout[20] = din[ 2] ^ din[15] ^ din[10];
dout[19] = din[ 1] ^ din[14] ^ din[ 9];
dout[18] = din[ 0] ^ din[13] ^ din[ 8];
dout[17] = din[22] ^ din[12] ^ din[17] ^ din[ 7];
dout[16] = din[21] ^ din[11] ^ din[16] ^ din[ 6];
dout[15] = din[20] ^ din[10] ^ din[15] ^ din[ 5];
dout[14] = din[19] ^ din[ 9] ^ din[14] ^ din[ 4];
dout[13] = din[18] ^ din[ 8] ^ din[13] ^ din[ 3];
dout[12] = din[17] ^ din[ 7] ^ din[12] ^ din[ 2];
dout[11] = din[16] ^ din[ 6] ^ din[11] ^ din[ 1];
dout[10] = din[15] ^ din[ 5] ^ din[10] ^ din[ 0];
dout[ 9] = din[14] ^ din[ 4] ^ din[ 9] ^ din[22] ^ din[17];
dout[ 8] = din[13] ^ din[ 3] ^ din[ 8] ^ din[21] ^ din[16];
dout[ 7] = din[12] ^ din[ 2] ^ din[ 7] ^ din[20] ^ din[15];
dout[ 6] = din[11] ^ din[ 1] ^ din[ 6] ^ din[19] ^ din[14];
dout[ 5] = din[10] ^ din[ 0] ^ din[ 5] ^ din[18] ^ din[13];
dout[ 4] = din[ 9] ^ din[22] ^ din[ 4] ^ din[12];
dout[ 3] = din[ 8] ^ din[21] ^ din[ 3] ^ din[11];
dout[ 2] = din[ 7] ^ din[20] ^ din[ 2] ^ din[10];
dout[ 1] = din[ 6] ^ din[19] ^ din[ 1] ^ din[ 9];
dout[ 0] = din[ 5] ^ din[18] ^ din[ 0] ^ din[ 8];
pn23 = dout;
end
endfunction
// PN9 function
function [63:0] pn9;
input [63:0] din;
reg [63:0] dout;
begin
dout[63] = din[ 8] ^ din[ 4];
dout[62] = din[ 7] ^ din[ 3];
dout[61] = din[ 6] ^ din[ 2];
dout[60] = din[ 5] ^ din[ 1];
dout[59] = din[ 4] ^ din[ 0];
dout[58] = din[ 3] ^ din[ 8] ^ din[ 4];
dout[57] = din[ 2] ^ din[ 7] ^ din[ 3];
dout[56] = din[ 1] ^ din[ 6] ^ din[ 2];
dout[55] = din[ 0] ^ din[ 5] ^ din[ 1];
dout[54] = din[ 8] ^ din[ 0];
dout[53] = din[ 7] ^ din[ 8] ^ din[ 4];
dout[52] = din[ 6] ^ din[ 7] ^ din[ 3];
dout[51] = din[ 5] ^ din[ 6] ^ din[ 2];
dout[50] = din[ 4] ^ din[ 5] ^ din[ 1];
dout[49] = din[ 3] ^ din[ 4] ^ din[ 0];
dout[48] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[47] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[46] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[45] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[44] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
dout[43] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
dout[42] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[41] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[40] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
dout[39] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
dout[38] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
dout[37] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
dout[36] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[35] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1];
dout[34] = din[ 6] ^ din[ 8] ^ din[ 0];
dout[33] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 4];
dout[32] = din[ 4] ^ din[ 6] ^ din[ 7] ^ din[ 3];
dout[31] = din[ 3] ^ din[ 5] ^ din[ 6] ^ din[ 2];
dout[30] = din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[29] = din[ 1] ^ din[ 3] ^ din[ 4] ^ din[ 0];
dout[28] = din[ 0] ^ din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[27] = din[ 8] ^ din[ 1] ^ din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 3];
dout[26] = din[ 7] ^ din[ 0] ^ din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 2];
dout[25] = din[ 6] ^ din[ 8] ^ din[ 0] ^ din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[24] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 1] ^ din[ 3] ^ din[ 0];
dout[23] = din[ 6] ^ din[ 7] ^ din[ 0] ^ din[ 2] ^ din[ 8];
dout[22] = din[ 5] ^ din[ 6] ^ din[ 8] ^ din[ 1] ^ din[ 4] ^ din[ 7];
dout[21] = din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 0] ^ din[ 3] ^ din[ 6];
dout[20] = din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 2] ^ din[ 5];
dout[19] = din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 1];
dout[18] = din[ 1] ^ din[ 4] ^ din[ 3] ^ din[ 6] ^ din[ 0];
dout[17] = din[ 0] ^ din[ 3] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[ 4];
dout[16] = din[ 8] ^ din[ 2] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[15] = din[ 7] ^ din[ 1] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[14] = din[ 6] ^ din[ 0] ^ din[ 8] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[13] = din[ 5] ^ din[ 8] ^ din[ 7] ^ din[ 3] ^ din[ 0];
dout[12] = din[ 7] ^ din[ 6] ^ din[ 2] ^ din[ 8];
dout[11] = din[ 6] ^ din[ 5] ^ din[ 1] ^ din[ 7];
dout[10] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6];
dout[ 9] = din[ 3] ^ din[ 8] ^ din[ 5];
dout[ 8] = din[ 2] ^ din[ 4] ^ din[ 7];
dout[ 7] = din[ 1] ^ din[ 3] ^ din[ 6];
dout[ 6] = din[ 0] ^ din[ 2] ^ din[ 5];
dout[ 5] = din[ 8] ^ din[ 1];
dout[ 4] = din[ 7] ^ din[ 0];
dout[ 3] = din[ 6] ^ din[ 8] ^ din[ 4];
dout[ 2] = din[ 5] ^ din[ 7] ^ din[ 3];
dout[ 1] = din[ 4] ^ din[ 6] ^ din[ 2];
dout[ 0] = din[ 3] ^ din[ 5] ^ din[ 1];
pn9 = dout;
end
endfunction
// pn sequence select
assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn;
always @(posedge adc_clk) begin
adc_pn_data_in <= { ~adc_data[15], adc_data[14: 0],
~adc_data[31], adc_data[30:16],
~adc_data[47], adc_data[46:32],
~adc_data[63], adc_data[62:48]};
if (adc_pnseq_sel == 4'd0) begin
adc_pn_data_pn <= pn9(adc_pn_data_pn_s);
end else begin
adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
end
end
// pn oos & pn err
ad_pnmon #(.DATA_WIDTH(64)) i_pnmon (
.adc_clk (adc_clk),
.adc_valid_in (1'b1),
.adc_data_in (adc_pn_data_in),
.adc_data_pn (adc_pn_data_pn),
.adc_pn_oos (adc_pn_oos),
.adc_pn_err (adc_pn_err));
endmodule
// ***************************************************************************
// ***************************************************************************