jesd204/scripts: fix indentation
Laszlo Nagy
István Csomortáni
parent
cf258ace83
commit
92d87c2d60
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@ -250,23 +250,23 @@ proc adi_tpl_jesd204_tx_create {ip_name num_of_lanes num_of_converters samples_p
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]
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if {$num_of_converters > 1} {
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# Concatenation and slicer cores
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ad_ip_instance xlconcat "${ip_name}/data_concat" [list \
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NUM_PORTS $num_of_converters \
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]
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# Concatenation and slicer cores
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ad_ip_instance xlconcat "${ip_name}/data_concat" [list \
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NUM_PORTS $num_of_converters \
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]
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for {set i 0} {$i < $num_of_converters} {incr i} {
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ad_ip_instance xlslice "${ip_name}/enable_slice_${i}" [list \
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DIN_WIDTH $num_of_converters \
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DIN_FROM $i \
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DIN_TO $i \
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]
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ad_ip_instance xlslice "${ip_name}/valid_slice_${i}" [list \
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DIN_WIDTH $num_of_converters \
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DIN_FROM $i \
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DIN_TO $i \
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]
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}
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for {set i 0} {$i < $num_of_converters} {incr i} {
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ad_ip_instance xlslice "${ip_name}/enable_slice_${i}" [list \
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DIN_WIDTH $num_of_converters \
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DIN_FROM $i \
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DIN_TO $i \
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]
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ad_ip_instance xlslice "${ip_name}/valid_slice_${i}" [list \
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DIN_WIDTH $num_of_converters \
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DIN_FROM $i \
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DIN_TO $i \
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]
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}
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}
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# Create connections
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# TPL configuration interface
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@ -280,16 +280,16 @@ proc adi_tpl_jesd204_tx_create {ip_name num_of_lanes num_of_converters samples_p
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# TPL - app layer
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if {$num_of_converters > 1} {
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for {set i 0} {$i < $num_of_converters} {incr i} {
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ad_connect ${ip_name}/tpl_core/enable ${ip_name}/enable_slice_$i/Din
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ad_connect ${ip_name}/tpl_core/dac_valid ${ip_name}/valid_slice_$i/Din
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for {set i 0} {$i < $num_of_converters} {incr i} {
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ad_connect ${ip_name}/tpl_core/enable ${ip_name}/enable_slice_$i/Din
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ad_connect ${ip_name}/tpl_core/dac_valid ${ip_name}/valid_slice_$i/Din
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ad_connect ${ip_name}/enable_slice_$i/Dout ${ip_name}/dac_enable_$i
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ad_connect ${ip_name}/valid_slice_$i/Dout ${ip_name}/dac_valid_$i
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ad_connect ${ip_name}/dac_data_$i ${ip_name}/data_concat/In$i
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ad_connect ${ip_name}/enable_slice_$i/Dout ${ip_name}/dac_enable_$i
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ad_connect ${ip_name}/valid_slice_$i/Dout ${ip_name}/dac_valid_$i
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ad_connect ${ip_name}/dac_data_$i ${ip_name}/data_concat/In$i
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}
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ad_connect ${ip_name}/data_concat/dout ${ip_name}/tpl_core/dac_ddata
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}
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ad_connect ${ip_name}/data_concat/dout ${ip_name}/tpl_core/dac_ddata
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} else {
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ad_connect ${ip_name}/dac_data_0 ${ip_name}/tpl_core/dac_ddata
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ad_connect ${ip_name}/tpl_core/enable ${ip_name}/dac_enable_0
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@ -365,25 +365,25 @@ proc adi_tpl_jesd204_rx_create {ip_name num_of_lanes num_of_converters samples_p
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]
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if {$num_of_converters > 1} {
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# Slicer cores
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for {set i 0} {$i < $num_of_converters} {incr i} {
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ad_ip_instance xlslice ${ip_name}/data_slice_$i [list \
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DIN_WIDTH [expr $sample_width*$samples_per_channel*$num_of_converters] \
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DIN_FROM [expr $sample_width*$samples_per_channel*($i+1)-1] \
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DIN_TO [expr $sample_width*$samples_per_channel*$i] \
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]
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# Slicer cores
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for {set i 0} {$i < $num_of_converters} {incr i} {
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ad_ip_instance xlslice ${ip_name}/data_slice_$i [list \
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DIN_WIDTH [expr $sample_width*$samples_per_channel*$num_of_converters] \
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DIN_FROM [expr $sample_width*$samples_per_channel*($i+1)-1] \
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DIN_TO [expr $sample_width*$samples_per_channel*$i] \
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]
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ad_ip_instance xlslice "${ip_name}/enable_slice_${i}" [list \
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DIN_WIDTH $num_of_converters \
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DIN_FROM $i \
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DIN_TO $i \
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]
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ad_ip_instance xlslice "${ip_name}/valid_slice_${i}" [list \
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DIN_WIDTH $num_of_converters \
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DIN_FROM $i \
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DIN_TO $i \
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]
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}
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ad_ip_instance xlslice "${ip_name}/enable_slice_${i}" [list \
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DIN_WIDTH $num_of_converters \
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DIN_FROM $i \
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DIN_TO $i \
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]
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ad_ip_instance xlslice "${ip_name}/valid_slice_${i}" [list \
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DIN_WIDTH $num_of_converters \
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DIN_FROM $i \
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DIN_TO $i \
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]
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}
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}
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# Create connections
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@ -401,16 +401,16 @@ proc adi_tpl_jesd204_rx_create {ip_name num_of_lanes num_of_converters samples_p
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# TPL - app layer
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if {$num_of_converters > 1} {
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for {set i 0} {$i < $num_of_converters} {incr i} {
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ad_connect ${ip_name}/tpl_core/adc_data ${ip_name}/data_slice_$i/Din
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ad_connect ${ip_name}/tpl_core/enable ${ip_name}/enable_slice_$i/Din
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ad_connect ${ip_name}/tpl_core/adc_valid ${ip_name}/valid_slice_$i/Din
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for {set i 0} {$i < $num_of_converters} {incr i} {
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ad_connect ${ip_name}/tpl_core/adc_data ${ip_name}/data_slice_$i/Din
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ad_connect ${ip_name}/tpl_core/enable ${ip_name}/enable_slice_$i/Din
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ad_connect ${ip_name}/tpl_core/adc_valid ${ip_name}/valid_slice_$i/Din
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ad_connect ${ip_name}/data_slice_$i/Dout ${ip_name}/adc_data_$i
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ad_connect ${ip_name}/enable_slice_$i/Dout ${ip_name}/adc_enable_$i
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ad_connect ${ip_name}/valid_slice_$i/Dout ${ip_name}/adc_valid_$i
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ad_connect ${ip_name}/data_slice_$i/Dout ${ip_name}/adc_data_$i
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ad_connect ${ip_name}/enable_slice_$i/Dout ${ip_name}/adc_enable_$i
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ad_connect ${ip_name}/valid_slice_$i/Dout ${ip_name}/adc_valid_$i
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}
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}
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} else {
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ad_connect ${ip_name}/tpl_core/adc_data ${ip_name}/adc_data_0
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ad_connect ${ip_name}/tpl_core/enable ${ip_name}/adc_enable_0
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