From 92aaf0bd51f807ac6967aff4d7db996fdf7b6676 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 12 Mar 2014 16:23:41 +0200 Subject: [PATCH] FMCOMMS1: Updated projects and axi_ad9643 core ZC702: Removed invalid address segments. Changed the constraints for adc_clk to minimum possible value in order to meet timing. ZED: Change the constraints for adc_clk to minimum possible value, in order to meet timing AXI_AD9643: Corrected the number of bits in the adc_mon_data bus --- library/axi_ad9643/axi_ad9643.v | 2 +- projects/fmcomms1/zc702/system_bd.tcl | 2 -- projects/fmcomms1/zc702/system_constr.xdc | 4 ++-- projects/fmcomms1/zed/system_constr.xdc | 4 ++-- 4 files changed, 5 insertions(+), 7 deletions(-) diff --git a/library/axi_ad9643/axi_ad9643.v b/library/axi_ad9643/axi_ad9643.v index 66b885ef8..b3df883a8 100755 --- a/library/axi_ad9643/axi_ad9643.v +++ b/library/axi_ad9643/axi_ad9643.v @@ -155,7 +155,7 @@ module axi_ad9643 ( // debug signals output adc_mon_valid; - output [28:0] adc_mon_data; + output [27:0] adc_mon_data; // internal registers diff --git a/projects/fmcomms1/zc702/system_bd.tcl b/projects/fmcomms1/zc702/system_bd.tcl index 56cfad62b..f2fb54afe 100644 --- a/projects/fmcomms1/zc702/system_bd.tcl +++ b/projects/fmcomms1/zc702/system_bd.tcl @@ -2,6 +2,4 @@ source $ad_hdl_dir/projects/common/zc702/zc702_system_bd.tcl source ../common/fmcomms1_bd.tcl -create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces axi_ad9643_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm -create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces axi_ad9122_dma/m_src_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm diff --git a/projects/fmcomms1/zc702/system_constr.xdc b/projects/fmcomms1/zc702/system_constr.xdc index b0d50e0d2..a81ceca98 100644 --- a/projects/fmcomms1/zc702/system_constr.xdc +++ b/projects/fmcomms1/zc702/system_constr.xdc @@ -83,9 +83,9 @@ set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_p # clocks create_clock -name dac_clk_in -period 2.10 [get_ports dac_clk_in_p] -create_clock -name adc_clk_in -period 4.00 [get_ports adc_clk_in_p] +create_clock -name adc_clk_in -period 4.06 [get_ports adc_clk_in_p] create_clock -name dac_div_clk -period 8.40 [get_pins i_system_wrapper/system_i/axi_ad9122/dac_div_clk] -create_clock -name adc_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_ad9643/adc_clk] +create_clock -name adc_clk -period 4.06 [get_pins i_system_wrapper/system_i/axi_ad9643/adc_clk] create_clock -name fmc_dma_clk -period 8.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2] set_clock_groups -asynchronous -group {dac_div_clk} diff --git a/projects/fmcomms1/zed/system_constr.xdc b/projects/fmcomms1/zed/system_constr.xdc index c3442963c..9b35b4324 100644 --- a/projects/fmcomms1/zed/system_constr.xdc +++ b/projects/fmcomms1/zed/system_constr.xdc @@ -83,9 +83,9 @@ set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_p # clocks create_clock -name dac_clk_in -period 2.10 [get_ports dac_clk_in_p] -create_clock -name adc_clk_in -period 4.00 [get_ports adc_clk_in_p] +create_clock -name adc_clk_in -period 4.06 [get_ports adc_clk_in_p] create_clock -name dac_div_clk -period 8.40 [get_pins i_system_wrapper/system_i/axi_ad9122/dac_div_clk] -create_clock -name adc_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_ad9643/adc_clk] +create_clock -name adc_clk -period 4.06 [get_pins i_system_wrapper/system_i/axi_ad9643/adc_clk] set_clock_groups -asynchronous -group {dac_div_clk} set_clock_groups -asynchronous -group {adc_clk}