diff --git a/library/util_adcfifo/util_adcfifo_hw.tcl b/library/util_adcfifo/util_adcfifo_hw.tcl index 23c4c7d26..14c6424bf 100644 --- a/library/util_adcfifo/util_adcfifo_hw.tcl +++ b/library/util_adcfifo/util_adcfifo_hw.tcl @@ -52,10 +52,15 @@ proc p_util_adcfifo {} { ad_alt_intf signal adc_wovf output 1 ovf ad_alt_intf clock dma_clk input 1 clk - ad_alt_intf signal dma_wr output 1 valid - ad_alt_intf signal dma_wdata output DMA_DATA_WIDTH data - ad_alt_intf signal dma_wready input 1 ready ad_alt_intf signal dma_xfer_req input 1 xfer_req ad_alt_intf signal dma_xfer_status output 4 xfer_status + + add_interface m_axis axi4stream start + set_interface_property m_axis associatedClock if_dma_clk + set_interface_property m_axis associatedReset if_adc_rst + add_interface_port m_axis dma_wr tvalid Output 1 + add_interface_port m_axis dma_wready tready Input 1 + add_interface_port m_axis dma_wdata tdata Output DMA_DATA_WIDTH + } diff --git a/library/util_dacfifo/util_dacfifo_hw.tcl b/library/util_dacfifo/util_dacfifo_hw.tcl index 3b481713d..dabca9b8c 100644 --- a/library/util_dacfifo/util_dacfifo_hw.tcl +++ b/library/util_dacfifo/util_dacfifo_hw.tcl @@ -23,11 +23,15 @@ ad_ip_parameter DATA_WIDTH INTEGER 128 ad_alt_intf clock dma_clk input 1 clk ad_alt_intf reset dma_rst input 1 if_dma_clk -ad_alt_intf signal dma_valid input 1 valid -ad_alt_intf signal dma_data input DATA_WIDTH data -ad_alt_intf signal dma_ready output 1 ready ad_alt_intf signal dma_xfer_req input 1 xfer_req -ad_alt_intf signal dma_xfer_last input 1 last + +add_interface s_axis axi4stream end +set_interface_property s_axis associatedClock if_dma_clk +set_interface_property s_axis associatedReset if_dma_rst +add_interface_port s_axis dma_valid tvalid Input 1 +add_interface_port s_axis dma_xfer_last tlast Input 1 +add_interface_port s_axis dma_ready tready Output 1 +add_interface_port s_axis dma_data tdata Input DATA_WIDTH ad_alt_intf clock dac_clk input 1 ad_alt_intf reset dac_rst input 1 if_dac_clk