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axi_fifo2s: fifo full replaced with ready

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Rejeesh Kutty 2014-11-12 14:42:08 -05:00
parent 5fc4f1b000
commit 925e966eb6
1 changed files with 1 additions and 1 deletions
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library/axi_fifo2s/axi_fifo2s_rd.v
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@ -163,7 +163,7 @@ module axi_fifo2s_rd (
// read is way too slow- buffer mode // read is way too slow- buffer mode
assign axi_ready_s = (~axi_arvalid | axi_arready) & ~axi_dready; assign axi_ready_s = (~axi_arvalid | axi_arready) & axi_dready;
always @(posedge axi_clk or negedge axi_resetn) begin always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin if (axi_resetn == 1'b0) begin