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axi_ad9684: Fixed up_drp_*data width

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AndreiGrozav 2016-10-12 13:02:54 +03:00
parent a505d304af
commit 91995c082d
2 changed files with 4 additions and 4 deletions
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4
library/axi_ad9684/axi_ad9684.v
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@ -187,8 +187,8 @@ module axi_ad9684 (
wire up_drp_sel_s;
wire up_drp_wr_s;
wire [11:0] up_drp_addr_s;
wire [15:0] up_drp_wdata_s;
wire [15:0] up_drp_rdata_s;
wire [31:0] up_drp_wdata_s;
wire [31:0] up_drp_rdata_s;
wire up_drp_ready_s;
wire up_drp_locked_s;
wire rst_s;

4
library/axi_ad9684/axi_ad9684_if.v
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@ -121,8 +121,8 @@ module axi_ad9684_if (
input up_drp_sel;
input up_drp_wr;
input [11:0] up_drp_addr;
input [15:0] up_drp_wdata;
output [15:0] up_drp_rdata;
input [31:0] up_drp_wdata;
output [31:0] up_drp_rdata;
output up_drp_ready;
output up_drp_locked;