From 91995c082d6f5c021c020a2afc36af7d06744575 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Wed, 12 Oct 2016 13:02:54 +0300 Subject: [PATCH] axi_ad9684: Fixed up_drp_*data width --- library/axi_ad9684/axi_ad9684.v | 4 ++-- library/axi_ad9684/axi_ad9684_if.v | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/library/axi_ad9684/axi_ad9684.v b/library/axi_ad9684/axi_ad9684.v index 8a0c51d27..b878bec4d 100644 --- a/library/axi_ad9684/axi_ad9684.v +++ b/library/axi_ad9684/axi_ad9684.v @@ -187,8 +187,8 @@ module axi_ad9684 ( wire up_drp_sel_s; wire up_drp_wr_s; wire [11:0] up_drp_addr_s; - wire [15:0] up_drp_wdata_s; - wire [15:0] up_drp_rdata_s; + wire [31:0] up_drp_wdata_s; + wire [31:0] up_drp_rdata_s; wire up_drp_ready_s; wire up_drp_locked_s; wire rst_s; diff --git a/library/axi_ad9684/axi_ad9684_if.v b/library/axi_ad9684/axi_ad9684_if.v index abceac525..d2672bf9a 100644 --- a/library/axi_ad9684/axi_ad9684_if.v +++ b/library/axi_ad9684/axi_ad9684_if.v @@ -121,8 +121,8 @@ module axi_ad9684_if ( input up_drp_sel; input up_drp_wr; input [11:0] up_drp_addr; - input [15:0] up_drp_wdata; - output [15:0] up_drp_rdata; + input [31:0] up_drp_wdata; + output [31:0] up_drp_rdata; output up_drp_ready; output up_drp_locked;