m2k: ip automatic version update
Adrian Costina
parent
ac5efc9adc
commit
919010e85f
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@ -24,120 +24,122 @@ create_bd_port -dir O -from 11 -to 0 txd
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# Logic analyzer (FCLK2): 100 MHz
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# Converter DMA (FCLK3): 55.6 MHz
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set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_CLK3_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {27.778}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {55.556}] $sys_ps7
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ad_ip_parameter sys_ps7 CONFIG.PCW_EN_CLK2_PORT 1
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ad_ip_parameter sys_ps7 CONFIG.PCW_EN_CLK3_PORT 1
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ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ 27.778
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ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ 100.0
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ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ 55.556
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ad_connect logic_analyzer_clk_in sys_ps7/FCLK_CLK2
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ad_connect converter_dma_clk sys_ps7/FCLK_CLK3
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set logic_analyzer [create_bd_cell -type ip -vlnv analog.com:user:axi_logic_analyzer:1.0 logic_analyzer]
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ad_ip_instance axi_logic_analyzer logic_analyzer
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set la_trigger_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_var_fifo:1.0 la_trigger_fifo]
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set_property -dict [list CONFIG.DATA_WIDTH {16} ] $la_trigger_fifo
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set_property -dict [list CONFIG.ADDRESS_WIDTH {13} ] $la_trigger_fifo
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ad_ip_instance util_var_fifo la_trigger_fifo
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ad_ip_parameter la_trigger_fifo CONFIG.DATA_WIDTH 16
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ad_ip_parameter la_trigger_fifo CONFIG.ADDRESS_WIDTH 13
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set bram_la [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 bram_la]
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set_property -dict [list CONFIG.use_bram_block {Stand_Alone}] $bram_la
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set_property -dict [list CONFIG.Memory_Type {Simple_Dual_Port_RAM}] $bram_la
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set_property -dict [list CONFIG.Assume_Synchronous_Clk {true}] $bram_la
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set_property -dict [list CONFIG.Algorithm {Low_Power}] $bram_la
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set_property -dict [list CONFIG.Use_Byte_Write_Enable {false}] $bram_la
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set_property -dict [list CONFIG.Operating_Mode_A {NO_CHANGE}] $bram_la
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set_property -dict [list CONFIG.Register_PortB_Output_of_Memory_Primitives {true}] $bram_la
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set_property -dict [list CONFIG.Use_RSTA_Pin {false} CONFIG.Port_B_Clock {100}] $bram_la
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set_property -dict [list CONFIG.Port_B_Enable_Rate {100}] $bram_la
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set_property -dict [list CONFIG.Write_Width_A {16}] $bram_la
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set_property -dict [list CONFIG.Write_Width_B {16}] $bram_la
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set_property -dict [list CONFIG.Read_Width_B {16}] $bram_la
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set_property -dict [list CONFIG.Write_Depth_A {8192}] $bram_la
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ad_ip_instance blk_mem_gen bram_la
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ad_ip_parameter bram_la CONFIG.use_bram_block {Stand_Alone}
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ad_ip_parameter bram_la CONFIG.Memory_Type {Simple_Dual_Port_RAM}
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ad_ip_parameter bram_la CONFIG.Assume_Synchronous_Clk {true}
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ad_ip_parameter bram_la CONFIG.Algorithm {Low_Power}
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ad_ip_parameter bram_la CONFIG.Use_Byte_Write_Enable {false}
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ad_ip_parameter bram_la CONFIG.Operating_Mode_A {NO_CHANGE}
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ad_ip_parameter bram_la CONFIG.Register_PortB_Output_of_Memory_Primitives {true}
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ad_ip_parameter bram_la CONFIG.Use_RSTA_Pin {false}
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ad_ip_parameter bram_la CONFIG.Port_B_Clock {100}
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ad_ip_parameter bram_la CONFIG.Port_B_Enable_Rate {100}
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ad_ip_parameter bram_la CONFIG.Write_Width_A {16}
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ad_ip_parameter bram_la CONFIG.Write_Width_B {16}
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ad_ip_parameter bram_la CONFIG.Read_Width_B {16}
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ad_ip_parameter bram_la CONFIG.Write_Depth_A {8192}
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set logic_analyzer_dmac [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 logic_analyzer_dmac]
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {16} ] $logic_analyzer_dmac
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set_property -dict [list CONFIG.DMA_AXI_PROTOCOL_DEST {1} ] $logic_analyzer_dmac
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set_property -dict [list CONFIG.SYNC_TRANSFER_START {true} ] $logic_analyzer_dmac
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set_property -dict [list CONFIG.DISABLE_DEBUG_REGISTERS $DISABLE_DMAC_DEBUG] $logic_analyzer_dmac
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ad_ip_instance axi_dmac logic_analyzer_dmac
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ad_ip_parameter logic_analyzer_dmac CONFIG.DMA_DATA_WIDTH_SRC 16
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ad_ip_parameter logic_analyzer_dmac CONFIG.DMA_AXI_PROTOCOL_DEST 1
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ad_ip_parameter logic_analyzer_dmac CONFIG.SYNC_TRANSFER_START true
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ad_ip_parameter logic_analyzer_dmac CONFIG.DISABLE_DEBUG_REGISTERS $DISABLE_DMAC_DEBUG
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set pattern_generator_dmac [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 pattern_generator_dmac]
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set_property -dict [list CONFIG.DMA_TYPE_DEST {2} ] $pattern_generator_dmac
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set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $pattern_generator_dmac
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set_property -dict [list CONFIG.MAX_BYTES_PER_BURST {128}] $pattern_generator_dmac
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set_property -dict [list CONFIG.DMA_AXI_PROTOCOL_SRC {1}] $pattern_generator_dmac
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {16} ] $pattern_generator_dmac
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $pattern_generator_dmac
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set_property -dict [list CONFIG.CYCLIC {true}] $pattern_generator_dmac
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set_property -dict [list CONFIG.DISABLE_DEBUG_REGISTERS $DISABLE_DMAC_DEBUG] $pattern_generator_dmac
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ad_ip_instance axi_dmac pattern_generator_dmac
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ad_ip_parameter pattern_generator_dmac CONFIG.DMA_TYPE_DEST 2
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ad_ip_parameter pattern_generator_dmac CONFIG.DMA_TYPE_SRC 0
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ad_ip_parameter pattern_generator_dmac CONFIG.MAX_BYTES_PER_BURST 128
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ad_ip_parameter pattern_generator_dmac CONFIG.DMA_AXI_PROTOCOL_SRC 1
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ad_ip_parameter pattern_generator_dmac CONFIG.DMA_DATA_WIDTH_DEST 16
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ad_ip_parameter pattern_generator_dmac CONFIG.DMA_DATA_WIDTH_SRC 64
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ad_ip_parameter pattern_generator_dmac CONFIG.CYCLIC true
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ad_ip_parameter pattern_generator_dmac CONFIG.DISABLE_DEBUG_REGISTERS $DISABLE_DMAC_DEBUG
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set axi_ad9963 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9963:1.0 axi_ad9963]
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set_property -dict [list CONFIG.DAC_DATAPATH_DISABLE {1}] $axi_ad9963
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set_property -dict [list CONFIG.ADC_DATAPATH_DISABLE {1}] $axi_ad9963
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ad_ip_instance axi_ad9963 axi_ad9963
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ad_ip_parameter axi_ad9963 CONFIG.DAC_DATAPATH_DISABLE 1
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ad_ip_parameter axi_ad9963 CONFIG.ADC_DATAPATH_DISABLE 1
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set adc_trigger_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_var_fifo:1.0 adc_trigger_fifo]
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set_property -dict [list CONFIG.DATA_WIDTH {32} ] $adc_trigger_fifo
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set_property -dict [list CONFIG.ADDRESS_WIDTH {13} ] $adc_trigger_fifo
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ad_ip_instance util_var_fifo adc_trigger_fifo
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ad_ip_parameter adc_trigger_fifo CONFIG.DATA_WIDTH 32
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ad_ip_parameter adc_trigger_fifo CONFIG.ADDRESS_WIDTH 13
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set bram_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 bram_adc]
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set_property -dict [list CONFIG.use_bram_block {Stand_Alone}] $bram_adc
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set_property -dict [list CONFIG.Memory_Type {Simple_Dual_Port_RAM}] $bram_adc
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set_property -dict [list CONFIG.Assume_Synchronous_Clk {true}] $bram_adc
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set_property -dict [list CONFIG.Algorithm {Low_Power}] $bram_adc
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set_property -dict [list CONFIG.Enable_32bit_Address {false}] $bram_adc
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set_property -dict [list CONFIG.Use_Byte_Write_Enable {false}] $bram_adc
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set_property -dict [list CONFIG.Operating_Mode_A {NO_CHANGE}] $bram_adc
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set_property -dict [list CONFIG.Register_PortB_Output_of_Memory_Primitives {true}] $bram_adc
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set_property -dict [list CONFIG.Use_RSTA_Pin {false} CONFIG.Port_B_Clock {100}] $bram_adc
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set_property -dict [list CONFIG.Port_B_Enable_Rate {100}] $bram_adc
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set_property -dict [list CONFIG.Write_Width_A {32}] $bram_adc
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set_property -dict [list CONFIG.Write_Width_B {32}] $bram_adc
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set_property -dict [list CONFIG.Read_Width_B {32}] $bram_adc
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set_property -dict [list CONFIG.Write_Depth_A {8192}] $bram_adc
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ad_ip_instance blk_mem_gen bram_adc
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ad_ip_parameter bram_adc CONFIG.use_bram_block {Stand_Alone}
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ad_ip_parameter bram_adc CONFIG.Memory_Type {Simple_Dual_Port_RAM}
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ad_ip_parameter bram_adc CONFIG.Assume_Synchronous_Clk true
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ad_ip_parameter bram_adc CONFIG.Algorithm {Low_Power}
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ad_ip_parameter bram_adc CONFIG.Enable_32bit_Address false
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ad_ip_parameter bram_adc CONFIG.Use_Byte_Write_Enable false
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ad_ip_parameter bram_adc CONFIG.Operating_Mode_A {NO_CHANGE}
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ad_ip_parameter bram_adc CONFIG.Register_PortB_Output_of_Memory_Primitives true
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ad_ip_parameter bram_adc CONFIG.Use_RSTA_Pin {false}
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ad_ip_parameter bram_adc CONFIG.Port_B_Clock 100
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ad_ip_parameter bram_adc CONFIG.Port_B_Enable_Rate 100
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ad_ip_parameter bram_adc CONFIG.Write_Width_A 32
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ad_ip_parameter bram_adc CONFIG.Write_Width_B 32
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ad_ip_parameter bram_adc CONFIG.Read_Width_B 32
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ad_ip_parameter bram_adc CONFIG.Write_Depth_A 8192
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set adc_trigger_extract [create_bd_cell -type ip -vlnv analog.com:user:util_extract:1.0 adc_trigger_extract]
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ad_ip_instance util_extract adc_trigger_extract
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# FIXME: Bring this back eventually
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#set util_cpack_ad9963 [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_cpack_ad9963]
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#set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_cpack_ad9963
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#set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_cpack_ad9963
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#ad_ip_instance util_cpack util_cpack_ad9963
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#ad_ip_parameter util_cpack_ad9963 CONFIG.NUM_OF_CHANNELS 2
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#ad_ip_parameter util_cpack_ad9963 CONFIG.CHANNEL_DATA_WIDTH 16
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create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 ad9963_adc_concat
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set ad9963_adc_dmac [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 ad9963_adc_dmac]
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32}] $ad9963_adc_dmac
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set_property -dict [list CONFIG.DMA_AXI_PROTOCOL_DEST {1}] $ad9963_adc_dmac
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set_property -dict [list CONFIG.SYNC_TRANSFER_START {true}] $ad9963_adc_dmac
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set_property -dict [list CONFIG.DISABLE_DEBUG_REGISTERS $DISABLE_DMAC_DEBUG] $ad9963_adc_dmac
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ad_ip_instance axi_dmac ad9963_adc_dmac
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ad_ip_parameter ad9963_adc_dmac CONFIG.DMA_DATA_WIDTH_SRC 32
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ad_ip_parameter ad9963_adc_dmac CONFIG.DMA_AXI_PROTOCOL_DEST 1
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ad_ip_parameter ad9963_adc_dmac CONFIG.SYNC_TRANSFER_START true
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ad_ip_parameter ad9963_adc_dmac CONFIG.DISABLE_DEBUG_REGISTERS $DISABLE_DMAC_DEBUG
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set ad9963_dac_dmac_a [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 ad9963_dac_dmac_a]
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set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $ad9963_dac_dmac_a
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set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $ad9963_dac_dmac_a
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set_property -dict [list CONFIG.DMA_AXI_PROTOCOL_SRC {1}] $ad9963_dac_dmac_a
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set_property -dict [list CONFIG.MAX_BYTES_PER_BURST {128}] $ad9963_dac_dmac_a
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {16}] $ad9963_dac_dmac_a
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $ad9963_dac_dmac_a
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set_property -dict [list CONFIG.CYCLIC {true}] $ad9963_dac_dmac_a
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set_property -dict [list CONFIG.DISABLE_DEBUG_REGISTERS $DISABLE_DMAC_DEBUG] $ad9963_dac_dmac_a
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ad_ip_instance axi_dmac ad9963_dac_dmac_a
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ad_ip_parameter ad9963_dac_dmac_a CONFIG.DMA_TYPE_DEST 2
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ad_ip_parameter ad9963_dac_dmac_a CONFIG.DMA_TYPE_SRC 0
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ad_ip_parameter ad9963_dac_dmac_a CONFIG.DMA_AXI_PROTOCOL_SRC 1
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ad_ip_parameter ad9963_dac_dmac_a CONFIG.MAX_BYTES_PER_BURST 128
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ad_ip_parameter ad9963_dac_dmac_a CONFIG.DMA_DATA_WIDTH_DEST 16
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ad_ip_parameter ad9963_dac_dmac_a CONFIG.DMA_DATA_WIDTH_SRC 64
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ad_ip_parameter ad9963_dac_dmac_a CONFIG.CYCLIC {true}
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ad_ip_parameter ad9963_dac_dmac_a CONFIG.DISABLE_DEBUG_REGISTERS $DISABLE_DMAC_DEBUG
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set ad9963_dac_dmac_b [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 ad9963_dac_dmac_b]
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set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $ad9963_dac_dmac_b
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set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $ad9963_dac_dmac_b
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set_property -dict [list CONFIG.DMA_AXI_PROTOCOL_SRC {1}] $ad9963_dac_dmac_b
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set_property -dict [list CONFIG.MAX_BYTES_PER_BURST {128}] $ad9963_dac_dmac_b
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {16}] $ad9963_dac_dmac_b
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $ad9963_dac_dmac_a
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set_property -dict [list CONFIG.CYCLIC {true}] $ad9963_dac_dmac_b
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set_property -dict [list CONFIG.DISABLE_DEBUG_REGISTERS $DISABLE_DMAC_DEBUG] $ad9963_dac_dmac_b
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ad_ip_instance axi_dmac ad9963_dac_dmac_b
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ad_ip_parameter ad9963_dac_dmac_b CONFIG.DMA_TYPE_DEST 2
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ad_ip_parameter ad9963_dac_dmac_b CONFIG.DMA_TYPE_SRC 0
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ad_ip_parameter ad9963_dac_dmac_b CONFIG.DMA_AXI_PROTOCOL_SRC 1
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ad_ip_parameter ad9963_dac_dmac_b CONFIG.MAX_BYTES_PER_BURST 128
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ad_ip_parameter ad9963_dac_dmac_b CONFIG.DMA_DATA_WIDTH_DEST 16
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ad_ip_parameter ad9963_dac_dmac_b CONFIG.DMA_DATA_WIDTH_SRC 64
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ad_ip_parameter ad9963_dac_dmac_b CONFIG.CYCLIC {true}
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ad_ip_parameter ad9963_dac_dmac_b CONFIG.DISABLE_DEBUG_REGISTERS $DISABLE_DMAC_DEBUG
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set adc_trigger [create_bd_cell -type ip -vlnv analog.com:user:axi_adc_trigger:1.0 adc_trigger]
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ad_ip_instance axi_adc_trigger adc_trigger
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set axi_adc_decimate [create_bd_cell -type ip -vlnv analog.com:user:axi_adc_decimate:1.0 axi_adc_decimate]
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set axi_dac_interpolate [create_bd_cell -type ip -vlnv analog.com:user:axi_dac_interpolate:1.0 axi_dac_interpolate]
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ad_ip_instance axi_adc_decimate axi_adc_decimate
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ad_ip_instance axi_dac_interpolate axi_dac_interpolate
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set logic_analyzer_reset [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 logic_analyzer_reset]
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ad_ip_instance proc_sys_reset logic_analyzer_reset
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set axi_rd_wr_combiner_logic [create_bd_cell -type ip -vlnv analog.com:user:axi_rd_wr_combiner:1.0 axi_rd_wr_combiner_logic]
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set axi_rd_wr_combiner_converter [create_bd_cell -type ip -vlnv analog.com:user:axi_rd_wr_combiner:1.0 axi_rd_wr_combiner_converter]
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ad_ip_instance axi_rd_wr_combiner axi_rd_wr_combiner_logic
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ad_ip_instance axi_rd_wr_combiner axi_rd_wr_combiner_converter
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ad_connect data_i logic_analyzer/data_i
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ad_connect trigger_i logic_analyzer/trigger_i
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@ -42,94 +42,92 @@ create_bd_port -dir I -type intr ps_intr_15
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# instance: sys_ps7
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set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7]
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ad_ip_instance processing_system7 sys_ps7
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set_property -dict [list CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V}] $sys_ps7
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set_property -dict [list CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V}] $sys_ps7
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set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_PACKAGE_NAME {clg225}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {17}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UART1_UART1_IO {MIO 12 .. 13}] $sys_ps7
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set_property -dict [list CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SD0_PERIPHERAL_ENABLE {0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
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set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USB0_RESET_IO {MIO 52}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USB0_RESET_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_PACKAGE_NAME {clg225}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP1 {1}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP2 {1}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_IO {17}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_UART1_UART1_IO {MIO 12 .. 13}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_PERIPHERAL_ENABLE {0}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_SPI0_SPI0_IO {EMIO}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_USE_FABRIC_INTERRUPT {1}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_RESET_IO {MIO 52}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_RESET_ENABLE {1}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_INTR {1}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_MODE {REVERSE}
|
||||
|
||||
# Clock the whole system of the DDR PLL, disable ARM and IO PLL
|
||||
# * PLL: 1000 MHz
|
||||
# * DDR: 500 MHz (2.0Gb/s),
|
||||
# * CPU: 500 MHz (downclocked to 250 MHz when idle)
|
||||
set_property -dict [list \
|
||||
CONFIG.PCW_OVERRIDE_BASIC_CLOCK {1} \
|
||||
CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
|
||||
CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \
|
||||
CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {20} \
|
||||
CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {16} \
|
||||
CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {6} \
|
||||
CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {40} \
|
||||
CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {40} \
|
||||
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {6} \
|
||||
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {6} \
|
||||
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {5} \
|
||||
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {2} \
|
||||
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {6} \
|
||||
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {3} \
|
||||
CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \
|
||||
CONFIG.PCW_ARMPLL_CTRL_FBDIV {30} \
|
||||
CONFIG.PCW_DDRPLL_CTRL_FBDIV {30} \
|
||||
CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {DDR PLL} \
|
||||
CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {DDR PLL} \
|
||||
CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {DDR PLL} \
|
||||
CONFIG.PCW_UART_PERIPHERAL_CLKSRC {DDR PLL} \
|
||||
CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {DDR PLL} \
|
||||
CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {DDR PLL} \
|
||||
CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {DDR PLL} \
|
||||
CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {DDR PLL} \
|
||||
CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {DDR PLL} \
|
||||
CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {DDR PLL} \
|
||||
CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {500} \
|
||||
CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {500}
|
||||
] [get_bd_cells sys_ps7]
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {DDR PLL}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {DDR PLL}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {DDR PLL}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_UART_PERIPHERAL_CLKSRC {DDR PLL}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {DDR PLL}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {DDR PLL}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {DDR PLL}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {DDR PLL}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {DDR PLL}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {DDR PLL}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {500}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {500}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_OVERRIDE_BASIC_CLOCK {1}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {20}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {16}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {6}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {40}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {40}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {6}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {6}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {5}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {2}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {6}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {3}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_IOPLL_CTRL_FBDIV {30}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_ARMPLL_CTRL_FBDIV {30}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_DDRPLL_CTRL_FBDIV {30}
|
||||
|
||||
# DDR MT41K256M16 HA-125 (32M, 16bit, 8banks)
|
||||
|
||||
set_property -dict [list CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.048}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.050}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.241}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.240}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {500.0}] $sys_ps7
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.048}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.050}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.241}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.240}
|
||||
ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {500.0}
|
||||
|
||||
set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
|
||||
ad_ip_instance axi_iic axi_iic_main
|
||||
|
||||
set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
|
||||
set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
|
||||
ad_ip_instance xlconcat sys_concat_intc
|
||||
ad_ip_parameter sys_concat_intc CONFIG.NUM_PORTS 16
|
||||
|
||||
set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
|
||||
set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen
|
||||
ad_ip_instance proc_sys_reset sys_rstgen
|
||||
ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1
|
||||
|
||||
# system reset/clock definitions
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue