prcfg: Update fmcomms2_pr for ZC706
parent
9dfbf4a9a6
commit
902d5b0da2
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@ -1,5 +1,5 @@
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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
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source $ad_hdl_dir/projects/fmcomms2/common/fmcomms2_bd.tcl
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source $ad_phdl_dir/projects/fmcomms2_rp/common/prcfg_setup.tcl
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source $ad_hdl_dir/projects/fmcomms2_rp/common/prcfg_setup.tcl
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@ -175,15 +175,17 @@ module system_top (
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wire clk;
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wire dma_dac_dunf;
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wire core_dac_dunf;
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wire [63:0] dma_dac_ddata;
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wire [63:0] core_dac_ddata;
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wire dma_dac_drd;
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wire core_dac_drd;
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wire [127:0] dma_dac_ddata;
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wire [127:0] core_dac_ddata;
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wire dma_dac_en;
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wire core_dac_en;
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wire dma_dac_dvalid;
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wire core_dac_dvalid;
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wire dma_adc_ovf;
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wire core_adc_ovf;
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wire [63:0] dma_adc_ddata;
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wire [63:0] core_adc_ddata;
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wire [127:0] dma_adc_ddata;
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wire [127:0] core_adc_ddata;
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wire dma_adc_dwr;
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wire core_adc_dwr;
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wire dma_adc_dsync;
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@ -216,12 +218,14 @@ module system_top (
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.adc_gpio_output(adc_gpio_output),
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.dac_gpio_input(dac_gpio_input),
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.dac_gpio_output(dac_gpio_output),
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.dma_dac_drd(dma_dac_drd),
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.dma_dac_en(dma_dac_en),
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.dma_dac_dunf(dma_dac_dunf),
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.dma_dac_ddata(dma_dac_ddata),
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.core_dac_drd(core_dac_drd),
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.dma_dac_dvalid(dma_dac_dvalid),
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.core_dac_en(core_dac_en),
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.core_dac_dunf(core_dac_dunf),
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.core_dac_ddata(core_dac_ddata),
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.core_dac_dvalid(core_dac_dvalid),
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.core_adc_dwr(core_adc_dwr),
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.core_adc_dsync(core_adc_dsync),
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.core_adc_ddata(core_adc_ddata),
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@ -295,12 +299,14 @@ module system_top (
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// pr related ports
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.clk(clk),
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.dma_dac_drd(dma_dac_drd),
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.dma_dac_en(dma_dac_en),
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.dma_dac_dunf(dma_dac_dunf),
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.dma_dac_ddata(dma_dac_ddata),
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.core_dac_drd(core_dac_drd),
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.dma_dac_dvalid(dma_dac_dvalid),
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.core_dac_en(core_dac_en),
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.core_dac_dunf(core_dac_dunf),
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.core_dac_ddata(core_dac_ddata),
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.core_dac_dvalid(core_dac_dvalid),
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.core_adc_dwr(core_adc_dwr),
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.core_adc_dsync(core_adc_dsync),
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@ -325,19 +331,21 @@ endmodule
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output [31:0] adc_gpio_output,
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input [31:0] dac_gpio_input,
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output [31:0] dac_gpio_output,
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output dma_dac_drd,
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output dma_dac_en,
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input dma_dac_dunf,
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input [63:0] dma_dac_ddata,
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input core_dac_drd,
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input [127:0] dma_dac_ddata,
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input dma_dac_dvalid,
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input core_dac_en,
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output core_dac_dunf,
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output [63:0] core_dac_ddata,
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output [127:0] core_dac_ddata,
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output core_dac_dvalid,
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input core_adc_dwr,
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input core_adc_dsync,
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input [63:0] core_adc_ddata,
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input [127:0] core_adc_ddata,
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output core_adc_ovf,
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output dma_adc_dwr,
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output dma_adc_dsync,
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output [63:0] dma_adc_ddata,
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output [127:0] dma_adc_ddata,
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input dma_adc_ovf);
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endmodule
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