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util_dec256sinc24b: Fix the differentiator 

Move the subtraction outside of the always block. In this way we're not adding
an additional delay element on to the output of the differentiator,
which brakes the transfer function of the filter.
main
Istvan Csomortani 2019-03-27 12:01:41 +00:00 committed by István Csomortáni
parent b46a28d42f
commit 8fb6fb329e
1 changed files with 18 additions and 20 deletions
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38
library/common/util_dec256sinc24b.v
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@ -51,15 +51,16 @@ module util_dec256sinc24b (
reg [36:0] acc2 = 37'h0; reg [36:0] acc2 = 37'h0;
reg [36:0] acc3 = 37'h0; reg [36:0] acc3 = 37'h0;
reg [36:0] acc3_d = 37'h0; reg [36:0] acc3_d = 37'h0;
reg [36:0] diff1 = 37'h0;
reg [36:0] diff2 = 37'h0;
reg [36:0] diff3 = 37'h0;
reg [36:0] diff1_d = 37'h0; reg [36:0] diff1_d = 37'h0;
reg [36:0] diff2_d = 37'h0; reg [36:0] diff2_d = 37'h0;
reg [15:0] word_count = 16'h0; reg [15:0] word_count = 16'h0;
reg word_en = 1'b0; reg word_en = 1'b0;
reg enable = 1'b0; reg enable = 1'b0;
wire [36:0] diff1_s;
wire [36:0] diff2_s;
wire [36:0] diff3_s;
/* Perform the Sinc action */ /* Perform the Sinc action */
always @(data_in) begin always @(data_in) begin
@ -120,18 +121,15 @@ module util_dec256sinc24b (
acc3_d <= 37'd0; acc3_d <= 37'd0;
diff1_d <= 37'd0; diff1_d <= 37'd0;
diff2_d <= 37'd0; diff2_d <= 37'd0;
diff1 <= 37'd0;
diff2 <= 37'd0;
diff3 <= 37'd0;
end else if (word_en == 1'b1) begin end else if (word_en == 1'b1) begin
diff1 <= acc3 - acc3_d;
diff2 <= diff1 - diff1_d;
diff3 <= diff2 - diff2_d;
acc3_d <= acc3; acc3_d <= acc3;
diff1_d <= diff1; diff1_d <= diff1_s;
diff2_d <= diff2; diff2_d <= diff2_s;
end end
end end
assign diff1_s = acc3 - acc3_d;
assign diff2_s = diff1_s - diff1_d;
assign diff3_s = diff2_s - diff2_d;
/* Clock the Sinc output into an output register /* Clock the Sinc output into an output register
* WORD_EN = output word rate */ * WORD_EN = output word rate */
@ -141,39 +139,39 @@ module util_dec256sinc24b (
case (dec_rate) case (dec_rate)
16'd32: begin 16'd32: begin
data_out <= (diff3[15:0] == 16'h8000) ? 16'hFFFF : {diff3[14:0], 1'b0}; data_out <= (diff3_s[15:0] == 16'h8000) ? 16'hFFFF : {diff3_s[14:0], 1'b0};
end end
16'd64: begin 16'd64: begin
data_out <= (diff3[18:2] == 17'h10000) ? 16'hFFFF : diff3[17:2]; data_out <= (diff3_s[18:2] == 17'h10000) ? 16'hFFFF : diff3_s[17:2];
end end
16'd128: begin 16'd128: begin
data_out <= (diff3[21:5] == 17'h10000) ? 16'hFFFF : diff3[20:5]; data_out <= (diff3_s[21:5] == 17'h10000) ? 16'hFFFF : diff3_s[20:5];
end end
16'd256: begin 16'd256: begin
data_out <= (diff3[24:8] == 17'h10000) ? 16'hFFFF : diff3[23:8]; data_out <= (diff3_s[24:8] == 17'h10000) ? 16'hFFFF : diff3_s[23:8];
end end
16'd512: begin 16'd512: begin
data_out <= (diff3[27:11] == 17'h10000) ? 16'hFFFF : diff3[26:11]; data_out <= (diff3_s[27:11] == 17'h10000) ? 16'hFFFF : diff3_s[26:11];
end end
16'd1024: begin 16'd1024: begin
data_out <= (diff3[30:14] == 17'h10000) ? 16'hFFFF : diff3[29:14]; data_out <= (diff3_s[30:14] == 17'h10000) ? 16'hFFFF : diff3_s[29:14];
end end
16'd2048: begin 16'd2048: begin
data_out <= (diff3[33:17] == 17'h10000) ? 16'hFFFF : diff3[32:17]; data_out <= (diff3_s[33:17] == 17'h10000) ? 16'hFFFF : diff3_s[32:17];
end end
16'd4096: begin 16'd4096: begin
data_out <= (diff3[36:20] == 17'h10000) ? 16'hFFFF : diff3[35:20]; data_out <= (diff3_s[36:20] == 17'h10000) ? 16'hFFFF : diff3_s[35:20];
end end
default:begin default:begin
data_out <= (diff3[24:8] == 17'h10000) ? 16'hFFFF : diff3[23:8]; data_out <= (diff3_s[24:8] == 17'h10000) ? 16'hFFFF : diff3_s[23:8];
end end
endcase endcase
end end