diff --git a/projects/fmcomms11/common/fmcomms11_bd.tcl b/projects/fmcomms11/common/fmcomms11_bd.tcl new file mode 100644 index 000000000..d9c58fdd2 --- /dev/null +++ b/projects/fmcomms11/common/fmcomms11_bd.tcl @@ -0,0 +1,223 @@ + +# daq2 + +create_bd_port -dir I rx_ref_clk +create_bd_port -dir O rx_sync +create_bd_port -dir I rx_sysref +create_bd_port -dir I -from 3 -to 0 rx_data_p +create_bd_port -dir I -from 3 -to 0 rx_data_n + +create_bd_port -dir I tx_ref_clk +create_bd_port -dir I tx_sync +create_bd_port -dir I tx_sysref +create_bd_port -dir O -from 3 -to 0 tx_data_p +create_bd_port -dir O -from 3 -to 0 tx_data_n + +# dac peripherals + +set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core] +set_property -dict [list CONFIG.QUAD_OR_DUAL_N {0}] $axi_ad9144_core + +set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9144_jesd] +set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd +set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9144_jesd + +set axi_ad9144_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9144_dma] +set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9144_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {1}] $axi_ad9144_dma +set_property -dict [list CONFIG.ID {1}] $axi_ad9144_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9144_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9144_dma +set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9144_dma +set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9144_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9144_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {128}] $axi_ad9144_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9144_dma + +set axi_ad9144_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 axi_ad9144_upack] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9144_upack +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9144_upack + +# adc peripherals + +set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core] + +set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9680_jesd] +set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd +set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd + +set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma] +set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9680_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.ID {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9680_dma +set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma +set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma + +set axi_ad9680_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad9680_cpack] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9680_cpack +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9680_cpack + +# dac/adc common gt + +set axi_daq2_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq2_gt] +set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_daq2_gt +set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_daq2_gt +set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $axi_daq2_gt +set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $axi_daq2_gt +set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_daq2_gt +set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_0 {1}] $axi_daq2_gt +set_property -dict [list CONFIG.TX_DATA_SEL_0 {0}] $axi_daq2_gt +set_property -dict [list CONFIG.TX_DATA_SEL_1 {3}] $axi_daq2_gt +set_property -dict [list CONFIG.TX_DATA_SEL_2 {1}] $axi_daq2_gt +set_property -dict [list CONFIG.TX_DATA_SEL_3 {2}] $axi_daq2_gt + +set util_daq2_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_daq2_gt] +set_property -dict [list CONFIG.QPLL0_ENABLE {1}] $util_daq2_gt +set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_daq2_gt +set_property -dict [list CONFIG.NUM_OF_LANES {4}] $util_daq2_gt +set_property -dict [list CONFIG.RX_ENABLE {1}] $util_daq2_gt +set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_daq2_gt +set_property -dict [list CONFIG.TX_ENABLE {1}] $util_daq2_gt +set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $util_daq2_gt + +# connections (gt) + +ad_connect util_daq2_gt/qpll_ref_clk rx_ref_clk +ad_connect util_daq2_gt/cpll_ref_clk tx_ref_clk + +ad_connect axi_daq2_gt/gt_qpll_0 util_daq2_gt/gt_qpll_0 +ad_connect axi_daq2_gt/gt_pll_0 util_daq2_gt/gt_pll_0 +ad_connect axi_daq2_gt/gt_pll_1 util_daq2_gt/gt_pll_1 +ad_connect axi_daq2_gt/gt_pll_2 util_daq2_gt/gt_pll_2 +ad_connect axi_daq2_gt/gt_pll_3 util_daq2_gt/gt_pll_3 +ad_connect axi_daq2_gt/gt_rx_0 util_daq2_gt/gt_rx_0 +ad_connect axi_daq2_gt/gt_rx_1 util_daq2_gt/gt_rx_1 +ad_connect axi_daq2_gt/gt_rx_2 util_daq2_gt/gt_rx_2 +ad_connect axi_daq2_gt/gt_rx_3 util_daq2_gt/gt_rx_3 +ad_connect axi_daq2_gt/gt_rx_ip_0 axi_ad9680_jesd/gt0_rx +ad_connect axi_daq2_gt/gt_rx_ip_1 axi_ad9680_jesd/gt1_rx +ad_connect axi_daq2_gt/gt_rx_ip_2 axi_ad9680_jesd/gt2_rx +ad_connect axi_daq2_gt/gt_rx_ip_3 axi_ad9680_jesd/gt3_rx +ad_connect axi_daq2_gt/rx_gt_comma_align_enb_0 axi_ad9680_jesd/rxencommaalign_out +ad_connect axi_daq2_gt/rx_gt_comma_align_enb_1 axi_ad9680_jesd/rxencommaalign_out +ad_connect axi_daq2_gt/rx_gt_comma_align_enb_2 axi_ad9680_jesd/rxencommaalign_out +ad_connect axi_daq2_gt/rx_gt_comma_align_enb_3 axi_ad9680_jesd/rxencommaalign_out +ad_connect axi_daq2_gt/gt_tx_0 util_daq2_gt/gt_tx_0 +ad_connect axi_daq2_gt/gt_tx_1 util_daq2_gt/gt_tx_1 +ad_connect axi_daq2_gt/gt_tx_2 util_daq2_gt/gt_tx_2 +ad_connect axi_daq2_gt/gt_tx_3 util_daq2_gt/gt_tx_3 +ad_connect axi_daq2_gt/gt_tx_ip_0 axi_ad9144_jesd/gt0_tx +ad_connect axi_daq2_gt/gt_tx_ip_1 axi_ad9144_jesd/gt1_tx +ad_connect axi_daq2_gt/gt_tx_ip_2 axi_ad9144_jesd/gt2_tx +ad_connect axi_daq2_gt/gt_tx_ip_3 axi_ad9144_jesd/gt3_tx + +# connections (dac) + +ad_connect util_daq2_gt/tx_sysref tx_sysref +ad_connect util_daq2_gt/tx_p tx_data_p +ad_connect util_daq2_gt/tx_n tx_data_n +ad_connect util_daq2_gt/tx_sync tx_sync +ad_connect util_daq2_gt/tx_out_clk util_daq2_gt/tx_clk +ad_connect util_daq2_gt/tx_out_clk axi_ad9144_jesd/tx_core_clk +ad_connect util_daq2_gt/tx_ip_rst axi_ad9144_jesd/tx_reset +ad_connect util_daq2_gt/tx_ip_rst_done axi_ad9144_jesd/tx_reset_done +ad_connect util_daq2_gt/tx_ip_sysref axi_ad9144_jesd/tx_sysref +ad_connect util_daq2_gt/tx_ip_sync axi_ad9144_jesd/tx_sync +ad_connect util_daq2_gt/tx_ip_data axi_ad9144_jesd/tx_tdata +ad_connect util_daq2_gt/tx_out_clk axi_ad9144_core/tx_clk +ad_connect util_daq2_gt/tx_data axi_ad9144_core/tx_data +ad_connect util_daq2_gt/tx_out_clk axi_ad9144_upack/dac_clk +ad_connect axi_ad9144_core/dac_enable_0 axi_ad9144_upack/dac_enable_0 +ad_connect axi_ad9144_core/dac_ddata_0 axi_ad9144_upack/dac_data_0 +ad_connect axi_ad9144_core/dac_valid_0 axi_ad9144_upack/dac_valid_0 +ad_connect axi_ad9144_core/dac_enable_1 axi_ad9144_upack/dac_enable_1 +ad_connect axi_ad9144_core/dac_ddata_1 axi_ad9144_upack/dac_data_1 +ad_connect axi_ad9144_core/dac_valid_1 axi_ad9144_upack/dac_valid_1 +ad_connect util_daq2_gt/tx_out_clk axi_ad9144_fifo/dac_clk +ad_connect axi_ad9144_upack/dac_valid axi_ad9144_fifo/dac_valid +ad_connect axi_ad9144_upack/dac_data axi_ad9144_fifo/dac_data +ad_connect axi_ad9144_upack/dma_xfer_in axi_ad9144_fifo/dac_xfer_out +ad_connect sys_cpu_clk axi_ad9144_fifo/dma_clk +ad_connect sys_cpu_reset axi_ad9144_fifo/dma_rst +ad_connect sys_cpu_clk axi_ad9144_dma/m_axis_aclk +ad_connect sys_cpu_resetn axi_ad9144_dma/m_src_axi_aresetn +ad_connect axi_ad9144_fifo/dma_xfer_req axi_ad9144_dma/m_axis_xfer_req +ad_connect axi_ad9144_fifo/dma_ready axi_ad9144_dma/m_axis_ready +ad_connect axi_ad9144_fifo/dma_data axi_ad9144_dma/m_axis_data +ad_connect axi_ad9144_fifo/dma_valid axi_ad9144_dma/m_axis_valid +ad_connect axi_ad9144_fifo/dma_xfer_last axi_ad9144_dma/m_axis_last + +# connections (adc) + +ad_connect util_daq2_gt/rx_sysref rx_sysref +ad_connect util_daq2_gt/rx_p rx_data_p +ad_connect util_daq2_gt/rx_n rx_data_n +ad_connect util_daq2_gt/rx_sync rx_sync +ad_connect util_daq2_gt/rx_out_clk util_daq2_gt/rx_clk +ad_connect util_daq2_gt/rx_out_clk axi_ad9680_jesd/rx_core_clk +ad_connect util_daq2_gt/rx_ip_rst axi_ad9680_jesd/rx_reset +ad_connect util_daq2_gt/rx_ip_rst_done axi_ad9680_jesd/rx_reset_done +ad_connect util_daq2_gt/rx_ip_sysref axi_ad9680_jesd/rx_sysref +ad_connect util_daq2_gt/rx_ip_sync axi_ad9680_jesd/rx_sync +ad_connect util_daq2_gt/rx_ip_sof axi_ad9680_jesd/rx_start_of_frame +ad_connect util_daq2_gt/rx_ip_data axi_ad9680_jesd/rx_tdata +ad_connect util_daq2_gt/rx_out_clk axi_ad9680_core/rx_clk +ad_connect util_daq2_gt/rx_data axi_ad9680_core/rx_data +ad_connect util_daq2_gt/rx_out_clk axi_ad9680_cpack/adc_clk +ad_connect util_daq2_gt/rx_rst axi_ad9680_cpack/adc_rst +ad_connect axi_ad9680_core/adc_enable_0 axi_ad9680_cpack/adc_enable_0 +ad_connect axi_ad9680_core/adc_valid_0 axi_ad9680_cpack/adc_valid_0 +ad_connect axi_ad9680_core/adc_data_0 axi_ad9680_cpack/adc_data_0 +ad_connect axi_ad9680_core/adc_enable_1 axi_ad9680_cpack/adc_enable_1 +ad_connect axi_ad9680_core/adc_valid_1 axi_ad9680_cpack/adc_valid_1 +ad_connect axi_ad9680_core/adc_data_1 axi_ad9680_cpack/adc_data_1 +ad_connect util_daq2_gt/rx_out_clk axi_ad9680_fifo/adc_clk +ad_connect util_daq2_gt/rx_rst axi_ad9680_fifo/adc_rst +ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr +ad_connect axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata +ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk +ad_connect sys_cpu_clk axi_ad9680_dma/s_axis_aclk +ad_connect sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn +ad_connect axi_ad9680_fifo/dma_wr axi_ad9680_dma/s_axis_valid +ad_connect axi_ad9680_fifo/dma_wdata axi_ad9680_dma/s_axis_data +ad_connect axi_ad9680_fifo/dma_wready axi_ad9680_dma/s_axis_ready +ad_connect axi_ad9680_fifo/dma_xfer_req axi_ad9680_dma/s_axis_xfer_req +ad_connect axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf + +# interconnect (cpu) + +ad_cpu_interconnect 0x44A60000 axi_daq2_gt +ad_cpu_interconnect 0x44A00000 axi_ad9144_core +ad_cpu_interconnect 0x44A90000 axi_ad9144_jesd +ad_cpu_interconnect 0x7c420000 axi_ad9144_dma +ad_cpu_interconnect 0x44A10000 axi_ad9680_core +ad_cpu_interconnect 0x44A91000 axi_ad9680_jesd +ad_cpu_interconnect 0x7c400000 axi_ad9680_dma + +# gt uses hp3, and 100MHz clock for both DRP and AXI4 + +ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3 +ad_mem_hp3_interconnect sys_cpu_clk axi_daq2_gt/m_axi + +# interconnect (mem/dac) + +ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1 +ad_mem_hp1_interconnect sys_cpu_clk axi_ad9144_dma/m_src_axi +ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2 +ad_mem_hp2_interconnect sys_cpu_clk axi_ad9680_dma/m_dest_axi + +# interrupts + +ad_cpu_interrupt ps-12 mb-13 axi_ad9144_dma/irq +ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq + +ad_connect axi_ad9144_core/dac_ddata_2 GND +ad_connect axi_ad9144_core/dac_ddata_3 GND + + diff --git a/projects/fmcomms11/zc706/Makefile b/projects/fmcomms11/zc706/Makefile new file mode 100644 index 000000000..ec2fa7313 --- /dev/null +++ b/projects/fmcomms11/zc706/Makefile @@ -0,0 +1,100 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += system_top.v +M_DEPS += system_project.tcl +M_DEPS += system_constr.xdc +M_DEPS += system_bd.tcl +M_DEPS += ../common/daq2_spi.v +M_DEPS += ../common/daq2_bd.tcl +M_DEPS += ../../scripts/adi_project.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_board.tcl +M_DEPS += ../../common/zc706/zc706_system_plddr3_adcfifo.tcl +M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc +M_DEPS += ../../common/zc706/zc706_system_mig.prj +M_DEPS += ../../common/zc706/zc706_system_constr.xdc +M_DEPS += ../../common/zc706/zc706_system_bd.tcl +M_DEPS += ../../common/xilinx/sys_dmafifo.tcl +M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr +M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr +M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr +M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr +M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr +M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr +M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr +M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr +M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr +M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr +M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr +M_DEPS += ../../../library/util_upack/util_upack.xpr + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.runs +M_FLIST += *.srcs +M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil + + + +.PHONY: all lib clean clean-all +all: lib daq2_zc706.sdk/system_top.hdf + + +clean: + rm -rf $(M_FLIST) + + +clean-all:clean + make -C ../../../library/axi_ad9144 clean + make -C ../../../library/axi_ad9680 clean + make -C ../../../library/axi_adcfifo clean + make -C ../../../library/axi_clkgen clean + make -C ../../../library/axi_dmac clean + make -C ../../../library/axi_hdmi_tx clean + make -C ../../../library/axi_jesd_gt clean + make -C ../../../library/axi_spdif_tx clean + make -C ../../../library/util_adcfifo clean + make -C ../../../library/util_cpack clean + make -C ../../../library/util_dacfifo clean + make -C ../../../library/util_jesd_gt clean + make -C ../../../library/util_upack clean + + +daq2_zc706.sdk/system_top.hdf: $(M_DEPS) + rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> daq2_zc706_vivado.log 2>&1 + + +lib: + make -C ../../../library/axi_ad9144 + make -C ../../../library/axi_ad9680 + make -C ../../../library/axi_adcfifo + make -C ../../../library/axi_clkgen + make -C ../../../library/axi_dmac + make -C ../../../library/axi_hdmi_tx + make -C ../../../library/axi_jesd_gt + make -C ../../../library/axi_spdif_tx + make -C ../../../library/util_adcfifo + make -C ../../../library/util_cpack + make -C ../../../library/util_dacfifo + make -C ../../../library/util_jesd_gt + make -C ../../../library/util_upack + +#################################################################################### +#################################################################################### diff --git a/projects/fmcomms11/zc706/system_bd.tcl b/projects/fmcomms11/zc706/system_bd.tcl new file mode 100644 index 000000000..44e72997e --- /dev/null +++ b/projects/fmcomms11/zc706/system_bd.tcl @@ -0,0 +1,25 @@ + +source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl +source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl +source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl + +p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10 +p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 + +create_bd_port -dir I -type rst sys_rst +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 +create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk + +set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst] + +ad_connect sys_rst axi_ad9680_fifo/sys_rst +ad_connect sys_clk axi_ad9680_fifo/sys_clk +ad_connect ddr3 axi_ad9680_fifo/ddr3 + +create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \ + [get_bd_addr_spaces axi_ad9680_fifo/axi_adcfifo/axi] \ + [get_bd_addr_segs axi_ad9680_fifo/axi_ddr_cntrl/memmap/memaddr] \ + SEG_axi_ddr_cntrl_memaddr + +source ../common/daq2_bd.tcl + diff --git a/projects/fmcomms11/zc706/system_constr.xdc b/projects/fmcomms11/zc706/system_constr.xdc new file mode 100644 index 000000000..df68021e6 --- /dev/null +++ b/projects/fmcomms11/zc706/system_constr.xdc @@ -0,0 +1,61 @@ + +# daq2 + +set_property -dict {PACKAGE_PIN AA8 } [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P +set_property -dict {PACKAGE_PIN AA7 } [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N +set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[0]] ; ## A10 FMC_HPC_DP3_M2C_P +set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[0]] ; ## A11 FMC_HPC_DP3_M2C_N +set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[1]] ; ## C06 FMC_HPC_DP0_M2C_P +set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[1]] ; ## C07 FMC_HPC_DP0_M2C_N +set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P +set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N +set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[3]] ; ## A02 FMC_HPC_DP1_M2C_P +set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[3]] ; ## A03 FMC_HPC_DP1_M2C_N +set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P +set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N +set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G09 FMC_HPC_LA03_P +set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G10 FMC_HPC_LA03_N + +set_property -dict {PACKAGE_PIN AD10} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P +set_property -dict {PACKAGE_PIN AD9 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N +set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[0]] ; ## A30 FMC_HPC_DP3_C2M_P (tx_data_p[0]) +set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[0]] ; ## A31 FMC_HPC_DP3_C2M_N (tx_data_n[0]) +set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[1]] ; ## C02 FMC_HPC_DP0_C2M_P (tx_data_p[3]) +set_property -dict {PACKAGE_PIN AK9 } [get_ports tx_data_n[1]] ; ## C03 FMC_HPC_DP0_C2M_N (tx_data_n[3]) +set_property -dict {PACKAGE_PIN AJ4 } [get_ports tx_data_p[2]] ; ## A26 FMC_HPC_DP2_C2M_P (tx_data_p[1]) +set_property -dict {PACKAGE_PIN AJ3 } [get_ports tx_data_n[2]] ; ## A27 FMC_HPC_DP2_C2M_N (tx_data_n[1]) +set_property -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[3]] ; ## A22 FMC_HPC_DP1_C2M_P (tx_data_p[2]) +set_property -dict {PACKAGE_PIN AK5 } [get_ports tx_data_n[3]] ; ## A23 FMC_HPC_DP1_C2M_N (tx_data_n[2]) +set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P +set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N +set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_p] ; ## H10 FMC_HPC_LA04_P +set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_n] ; ## H11 FMC_HPC_LA04_N + +set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk] ; ## D11 FMC_HPC_LA05_P +set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports spi_csn_dac] ; ## C14 FMC_HPC_LA10_P +set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports spi_csn_adc] ; ## D15 FMC_HPC_LA09_N +set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D12 FMC_HPC_LA05_N +set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## D14 FMC_HPC_LA09_P +set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports spi_dir] ; ## G13 FMC_HPC_LA08_N + +set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports clkd_sync] ; ## G12 FMC_HPC_LA08_P +set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports dac_reset] ; ## C15 FMC_HPC_LA10_N +set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports dac_txen] ; ## G16 FMC_HPC_LA12_N +set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports adc_pd] ; ## C10 FMC_HPC_LA06_P + +set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports clkd_status[0]] ; ## D17 FMC_HPC_LA13_P +set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports clkd_status[1]] ; ## D18 FMC_HPC_LA13_N +set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports dac_irq] ; ## G15 FMC_HPC_LA12_P +set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports adc_fda] ; ## H16 FMC_HPC_LA11_P +set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports adc_fdb] ; ## H17 FMC_HPC_LA11_N + +set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_p] ; ## H13 FMC_HPC_LA07_P +set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_n] ; ## H14 FMC_HPC_LA07_N + +# clocks + +create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p] +create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p] +create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK] +create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] + diff --git a/projects/fmcomms11/zc706/system_project.tcl b/projects/fmcomms11/zc706/system_project.tcl new file mode 100644 index 000000000..8d6209938 --- /dev/null +++ b/projects/fmcomms11/zc706/system_project.tcl @@ -0,0 +1,22 @@ + + + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project_create daq2_zc706 +adi_project_files daq2_zc706 [list \ + "../common/daq2_spi.v" \ + "system_top.v" \ + "system_constr.xdc"\ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \ + "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] + +set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc] +set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] + +adi_project_run daq2_zc706 + + diff --git a/projects/fmcomms11/zc706/system_top.v b/projects/fmcomms11/zc706/system_top.v new file mode 100644 index 000000000..071300f3a --- /dev/null +++ b/projects/fmcomms11/zc706/system_top.v @@ -0,0 +1,425 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + ddr_addr, + ddr_ba, + ddr_cas_n, + ddr_ck_n, + ddr_ck_p, + ddr_cke, + ddr_cs_n, + ddr_dm, + ddr_dq, + ddr_dqs_n, + ddr_dqs_p, + ddr_odt, + ddr_ras_n, + ddr_reset_n, + ddr_we_n, + + fixed_io_ddr_vrn, + fixed_io_ddr_vrp, + fixed_io_mio, + fixed_io_ps_clk, + fixed_io_ps_porb, + fixed_io_ps_srstb, + + gpio_bd, + + hdmi_out_clk, + hdmi_vsync, + hdmi_hsync, + hdmi_data_e, + hdmi_data, + + spdif, + + sys_rst, + sys_clk_p, + sys_clk_n, + + ddr3_addr, + ddr3_ba, + ddr3_cas_n, + ddr3_ck_n, + ddr3_ck_p, + ddr3_cke, + ddr3_cs_n, + ddr3_dm, + ddr3_dq, + ddr3_dqs_n, + ddr3_dqs_p, + ddr3_odt, + ddr3_ras_n, + ddr3_reset_n, + ddr3_we_n, + + iic_scl, + iic_sda, + + rx_ref_clk_p, + rx_ref_clk_n, + rx_sysref_p, + rx_sysref_n, + rx_sync_p, + rx_sync_n, + rx_data_p, + rx_data_n, + + tx_ref_clk_p, + tx_ref_clk_n, + tx_sysref_p, + tx_sysref_n, + tx_sync_p, + tx_sync_n, + tx_data_p, + tx_data_n, + + trig_p, + trig_n, + + adc_fdb, + adc_fda, + dac_irq, + clkd_status, + + adc_pd, + dac_txen, + dac_reset, + clkd_sync, + + spi_csn_clk, + spi_csn_dac, + spi_csn_adc, + spi_clk, + spi_sdio, + spi_dir); + + inout [14:0] ddr_addr; + inout [ 2:0] ddr_ba; + inout ddr_cas_n; + inout ddr_ck_n; + inout ddr_ck_p; + inout ddr_cke; + inout ddr_cs_n; + inout [ 3:0] ddr_dm; + inout [31:0] ddr_dq; + inout [ 3:0] ddr_dqs_n; + inout [ 3:0] ddr_dqs_p; + inout ddr_odt; + inout ddr_ras_n; + inout ddr_reset_n; + inout ddr_we_n; + + inout fixed_io_ddr_vrn; + inout fixed_io_ddr_vrp; + inout [53:0] fixed_io_mio; + inout fixed_io_ps_clk; + inout fixed_io_ps_porb; + inout fixed_io_ps_srstb; + + inout [14:0] gpio_bd; + + output hdmi_out_clk; + output hdmi_vsync; + output hdmi_hsync; + output hdmi_data_e; + output [23:0] hdmi_data; + + output spdif; + + input sys_rst; + input sys_clk_p; + input sys_clk_n; + + output [13:0] ddr3_addr; + output [ 2:0] ddr3_ba; + output ddr3_cas_n; + output [ 0:0] ddr3_ck_n; + output [ 0:0] ddr3_ck_p; + output [ 0:0] ddr3_cke; + output [ 0:0] ddr3_cs_n; + output [ 7:0] ddr3_dm; + inout [63:0] ddr3_dq; + inout [ 7:0] ddr3_dqs_n; + inout [ 7:0] ddr3_dqs_p; + output [ 0:0] ddr3_odt; + output ddr3_ras_n; + output ddr3_reset_n; + output ddr3_we_n; + + inout iic_scl; + inout iic_sda; + + input rx_ref_clk_p; + input rx_ref_clk_n; + input rx_sysref_p; + input rx_sysref_n; + output rx_sync_p; + output rx_sync_n; + input [ 3:0] rx_data_p; + input [ 3:0] rx_data_n; + + input tx_ref_clk_p; + input tx_ref_clk_n; + input tx_sysref_p; + input tx_sysref_n; + input tx_sync_p; + input tx_sync_n; + output [ 3:0] tx_data_p; + output [ 3:0] tx_data_n; + + input trig_p; + input trig_n; + + inout adc_fdb; + inout adc_fda; + inout dac_irq; + inout [ 1:0] clkd_status; + + inout adc_pd; + inout dac_txen; + inout dac_reset; + inout clkd_sync; + + output spi_csn_clk; + output spi_csn_dac; + output spi_csn_adc; + output spi_clk; + inout spi_sdio; + output spi_dir; + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire [ 2:0] spi0_csn; + wire spi0_clk; + wire spi0_mosi; + wire spi0_miso; + wire [ 2:0] spi1_csn; + wire spi1_clk; + wire spi1_mosi; + wire spi1_miso; + wire trig; + wire rx_ref_clk; + wire rx_sysref; + wire rx_sync; + wire tx_ref_clk; + wire tx_sysref; + wire tx_sync; + + // spi + + assign spi_csn_adc = spi0_csn[2]; + assign spi_csn_dac = spi0_csn[1]; + assign spi_csn_clk = spi0_csn[0]; + + // instantiations + + IBUFDS_GTE2 i_ibufds_rx_ref_clk ( + .CEB (1'd0), + .I (rx_ref_clk_p), + .IB (rx_ref_clk_n), + .O (rx_ref_clk), + .ODIV2 ()); + + IBUFDS i_ibufds_rx_sysref ( + .I (rx_sysref_p), + .IB (rx_sysref_n), + .O (rx_sysref)); + + OBUFDS i_obufds_rx_sync ( + .I (rx_sync), + .O (rx_sync_p), + .OB (rx_sync_n)); + + IBUFDS_GTE2 i_ibufds_tx_ref_clk ( + .CEB (1'd0), + .I (tx_ref_clk_p), + .IB (tx_ref_clk_n), + .O (tx_ref_clk), + .ODIV2 ()); + + IBUFDS i_ibufds_tx_sysref ( + .I (tx_sysref_p), + .IB (tx_sysref_n), + .O (tx_sysref)); + + IBUFDS i_ibufds_tx_sync ( + .I (tx_sync_p), + .IB (tx_sync_n), + .O (tx_sync)); + + daq2_spi i_spi ( + .spi_csn (spi0_csn), + .spi_clk (spi_clk), + .spi_mosi (spi0_mosi), + .spi_miso (spi0_miso), + .spi_sdio (spi_sdio), + .spi_dir (spi_dir)); + + IBUFDS i_ibufds_trig ( + .I (trig_p), + .IB (trig_n), + .O (trig)); + + assign gpio_i[43] = trig; + assign spi_clk = spi0_clk; + + ad_iobuf #(.DATA_WIDTH(9)) i_iobuf ( + .dio_t ({gpio_t[42:40], gpio_t[38], gpio_t[36:32]}), + .dio_i ({gpio_o[42:40], gpio_o[38], gpio_o[36:32]}), + .dio_o ({gpio_i[42:40], gpio_i[38], gpio_i[36:32]}), + .dio_p ({ adc_pd, // 42 + dac_txen, // 41 + dac_reset, // 40 + clkd_sync, // 38 + adc_fdb, // 36 + adc_fda, // 35 + dac_irq, // 34 + clkd_status})); // 32 + + ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd ( + .dio_t (gpio_t[14:0]), + .dio_i (gpio_o[14:0]), + .dio_o (gpio_i[14:0]), + .dio_p (gpio_bd)); + + system_wrapper i_system_wrapper ( + .ddr3_addr (ddr3_addr), + .ddr3_ba (ddr3_ba), + .ddr3_cas_n (ddr3_cas_n), + .ddr3_ck_n (ddr3_ck_n), + .ddr3_ck_p (ddr3_ck_p), + .ddr3_cke (ddr3_cke), + .ddr3_cs_n (ddr3_cs_n), + .ddr3_dm (ddr3_dm), + .ddr3_dq (ddr3_dq), + .ddr3_dqs_n (ddr3_dqs_n), + .ddr3_dqs_p (ddr3_dqs_p), + .ddr3_odt (ddr3_odt), + .ddr3_ras_n (ddr3_ras_n), + .ddr3_reset_n (ddr3_reset_n), + .ddr3_we_n (ddr3_we_n), + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_10 (1'b0), + .ps_intr_11 (1'b0), + .rx_data_n (rx_data_n), + .rx_data_p (rx_data_p), + .rx_ref_clk (rx_ref_clk), + .rx_sync (rx_sync), + .rx_sysref (rx_sysref), + .spdif (spdif), + .spi0_clk_i (spi0_clk), + .spi0_clk_o (spi0_clk), + .spi0_csn_0_o (spi0_csn[0]), + .spi0_csn_1_o (spi0_csn[1]), + .spi0_csn_2_o (spi0_csn[2]), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi0_miso), + .spi0_sdo_i (spi0_mosi), + .spi0_sdo_o (spi0_mosi), + .spi1_clk_i (spi1_clk), + .spi1_clk_o (spi1_clk), + .spi1_csn_0_o (spi1_csn[0]), + .spi1_csn_1_o (spi1_csn[1]), + .spi1_csn_2_o (spi1_csn[2]), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b1), + .spi1_sdo_i (spi1_mosi), + .spi1_sdo_o (spi1_mosi), + .sys_clk_clk_n (sys_clk_n), + .sys_clk_clk_p (sys_clk_p), + .sys_rst (sys_rst), + .tx_data_n (tx_data_n), + .tx_data_p (tx_data_p), + .tx_ref_clk (tx_ref_clk), + .tx_sync (tx_sync), + .tx_sysref (tx_sysref)); + +endmodule + +// *************************************************************************** +// ***************************************************************************