From 8ecdb4a4ca376fb133ee666d9667e2560715d72e Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Fri, 16 Oct 2015 11:55:22 +0300 Subject: [PATCH] library/tdd_control: Add common registers to the register map and fix init value of a register + Software in general needs to have access to the VERSION register. + tdd_sync_d3 registers init value should be 1'b0 --- library/common/ad_tdd_control.v | 2 +- library/common/up_tdd_cntrl.v | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/library/common/ad_tdd_control.v b/library/common/ad_tdd_control.v index 19de94e15..0fe8f85fc 100644 --- a/library/common/ad_tdd_control.v +++ b/library/common/ad_tdd_control.v @@ -226,7 +226,7 @@ module ad_tdd_control( // edge detection circuit always @(posedge clk) begin if (rst == 1'b1) begin - tdd_sync_d3 <= 1'b1; + tdd_sync_d3 <= 1'b0; tdd_sync_pulse <= 1'b0; end else begin tdd_sync_d3 <= tdd_sync_d2; diff --git a/library/common/up_tdd_cntrl.v b/library/common/up_tdd_cntrl.v index 87f26cb49..d51f750df 100644 --- a/library/common/up_tdd_cntrl.v +++ b/library/common/up_tdd_cntrl.v @@ -241,6 +241,9 @@ module up_tdd_cntrl ( up_tdd_tx_dp_on_2 <= 24'h0; end else begin up_wack <= up_wreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin + up_scratch <= up_wdata; + end if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin up_tdd_enable <= up_wdata[0]; up_tdd_secondary <= up_wdata[1]; @@ -338,6 +341,9 @@ module up_tdd_cntrl ( up_rack <= up_rreq_s; if (up_rreq_s == 1'b1) begin case (up_raddr[7:0]) + 8'h00: up_rdata <= PCORE_VERSION; + 8'h01: up_rdata <= ID; + 8'h02: up_rdata <= up_scratch; 8'h10: up_rdata <= {28'h0, up_tdd_gated_tx_dmapath, up_tdd_gated_rx_dmapath, up_tdd_tx_only,