adi_board.tcl: All procedures works on Zynq/Microblaze
General patch for the integration procedures. Tested on kc705 and zed.main
Istvan Csomortani
parent
9676146725
commit
8deb36ce08
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@ -11,14 +11,14 @@ proc set_num {number} {
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}
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}
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# search the first free HP port in case of a Zynq device
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proc free_hp_port {} {
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proc free_hp_port { sys_ps7 } {
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set hp_port_num 0
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set hp_port 1
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while(hp_port) {
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set hp_port_num [expr hp_port_num + 1]
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set hp_port [get_property "CONFIG.PCW_USE_S_AXI_HP${hp_port_num}" [get_bd_cells sys_ps7]]
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while { $hp_port == 1 } {
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set hp_port_num [expr $hp_port_num + 1]
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set hp_port [get_property "CONFIG.PCW_USE_S_AXI_HP${hp_port_num}" $sys_ps7]
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}
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return $hp_port_num
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@ -42,9 +42,6 @@ proc adi_interconnect_lite { peripheral_name peripheral_address } {
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# check processor type, connect system clock and reset to the peripheral
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if { $::sys_zynq == 1 } {
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# sys_proc is a zynq
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set sys_proc [get_bd_cells sys_ps7]
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# connect clk and reset for the interconnect
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connect_bd_net -net sys_100m_clk \
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[get_bd_pins "$interconnect_bd/M[set_num [expr $number_of_master -1]]_ACLK"] $::sys_100m_clk_source
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@ -57,13 +54,10 @@ proc adi_interconnect_lite { peripheral_name peripheral_address } {
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connect_bd_net -net sys_100m_resetn \
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[get_bd_pins "${peripheral_name}/s_axi_aresetn"]
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} else {
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# sys_proc is a micorblaze
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set sys_proc [get_bd_cells sys_mb]
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# connect clk and reset for the interconnect
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connect_bd_net -net sys_100m_clk \
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[get_bd_pins "$interconnect_bd/M[set_num [expr $number_of_master -1]]_ACLK"] $::sys_100m_clk_source
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connect_bd_net -net sys_100m_resetn_intc \
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connect_bd_net -net sys_100m_resetn \
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[get_bd_pins "$interconnect_bd/M[set_num [expr $number_of_master -1]]_ARESETN"] $::sys_100m_resetn_source
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# connect clk and reset for the peripheral port
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@ -109,12 +103,10 @@ proc adi_spi_core { spi_name spi_ss_width spi_base_addr } {
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# check processor type, connect system clock and reset to the peripheral
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if { $::sys_zynq == 1 } {
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# sys_proc is a zynq
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set sys_proc [get_bd_cells sys_ps7]
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# add SPI interface to ps7
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set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_proc
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set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_proc
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set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] [get_bd_cells sys_ps7]
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set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] [get_bd_cells sys_ps7]
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set i 0
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while { $i < $spi_ss_width } {
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@ -155,58 +147,76 @@ proc adi_spi_core { spi_name spi_ss_width spi_base_addr } {
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[get_bd_ports spi_csn_i] \
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[get_bd_pins sys_ps7/SPI0_SS_I]
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connect_bd_net -net spi_sclk_i \
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[get_bd_ports spi_clk_i] \
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[get_bd_ports spi_sclk_i] \
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[get_bd_pins sys_ps7/SPI0_SCLK_I]
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connect_bd_net -net spi_sclk_o \
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[get_bd_ports spi_clk_o] \
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[get_bd_ports spi_sclk_o] \
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[get_bd_pins sys_ps7/SPI0_SCLK_O]
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connect_bd_net -net spi_mosi_i \
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[get_bd_ports spi_sdo_i] \
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[get_bd_ports spi_mosi_i] \
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[get_bd_pins sys_ps7/SPI0_MOSI_I]
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connect_bd_net -net spi_mosi_o \
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[get_bd_ports spi_sdo_o] \
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[get_bd_ports spi_mosi_o] \
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[get_bd_pins sys_ps7/SPI0_MOSI_O]
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connect_bd_net -net spi_miso_i \
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[get_bd_ports spi_sdi_i] \
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[get_bd_ports spi_miso_i] \
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[get_bd_pins sys_ps7/SPI0_MISO_I]
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} else {
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# SPI SS lines
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set spi_csn_i [create_bd_port -dir I -from [expr $spi_ss_width - 1] -to 0 spi_csn_i]
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set spi_csn_o [create_bd_port -dir O -from [expr $spi_ss_width - 1] -to 0 spi_csn_o]
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# instanciate AXI_SPI core
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set spi_name [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 $spi_name]
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set_property -dict [list CONFIG.C_USE_STARTUP {0}] $spi_name
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set_property -dict [list CONFIG.C_NUM_SS_BITS {$spi_ss_width}] $spi_name
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set_property -dict [list CONFIG.C_SCK_RATIO {16}] $spi_name
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set_property -dict [list CONFIG.Multiples16 {2}] $spi_name
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switch $spi_ss_width {
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1
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{
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set_property -dict [list CONFIG.C_NUM_SS_BITS {1}] $spi_name
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}
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2
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{
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set_property -dict [list CONFIG.C_NUM_SS_BITS {2}] $spi_name
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}
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3
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{
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set_property -dict [list CONFIG.C_NUM_SS_BITS {3}] $spi_name
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}
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4
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{
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set_property -dict [list CONFIG.C_NUM_SS_BITS {4}] $spi_name
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}
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}
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adi_interconnect_lite $spi_name $spi_base_addr
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connect_bd_net -net sys_100m_clk \
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[get_bd_pins "${spi_name}/ext_spi_clk"] \
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$::sys_100m_clk_source
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# spi external ports
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connect_bd_net -net spi_csn_o \
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[get_bd_ports spi_csn_o] \
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[get_bd_pins "${spi_name}/ss_i"]
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[get_bd_pins "${spi_name}/ss_o"]
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connect_bd_net -net spi_csn_i \
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[get_bd_ports spi_csn_i] \
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[get_bd_pins "${spi_name}/ss_o"]
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[get_bd_pins "${spi_name}/ss_i"]
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connect_bd_net -net spi_sclk_o \
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[get_bd_ports spi_clk_o] \
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[get_bd_ports spi_sclk_o] \
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[get_bd_pins "${spi_name}/sck_o"]
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connect_bd_net -net spi_sclk_i \
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[get_bd_ports spi_clk_i] \
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[get_bd_ports spi_sclk_i] \
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[get_bd_pins "${spi_name}/sck_i"]
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connect_bd_net -net spi_mosi_o \
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[get_bd_pins spi_sdo_o] \
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[get_bd_ports spi_mosi_o] \
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[get_bd_pins "${spi_name}/io0_o"]
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connect_bd_net -net spi_mosi_i \
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[get_bd_pins spi_sdo_i] \
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[get_bd_ports spi_mosi_i] \
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[get_bd_pins "${spi_name}/io0_i"]
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connect_bd_net -net spi_miso_i \
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[get_bd_ports spi_sdi_i] \
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[get_bd_ports spi_miso_i] \
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[get_bd_pins "${spi_name}/io1_i"]
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create_bd_addr_seg -range 0x00010000 -offset $spi_base_addr
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$::sys_addr_cntrl_space \
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[get_bd_addr_segs "${spi_name}/axi_lite/Reg"] \
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"SEG_data_${spi_name}"
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}
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}
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@ -215,43 +225,59 @@ proc adi_dma_interconnect { dma_name port_name} {
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# check processor type, connect system clock and reset to the peripheral
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if { $::sys_zynq == 1 } {
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set hp_port [free_hp_port]
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set_property -dict [list "CONFIG.PCW_USE_S_AXI_HP${hp_port}" {1}] $sys_ps7
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set axi_dma_interconnect_($hp_port) [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_dma_interconnect_($hp_port)]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_dma_interconnect_($hp_port)
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set hp_port [free_hp_port [get_bd_cells sys_ps7]]
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set_property -dict [list "CONFIG.PCW_USE_S_AXI_HP${hp_port}" {1}] [get_bd_cells sys_ps7]
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switch $hp_port {
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1
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{
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set axi_dma_interconnect_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_dma_interconnect_1]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_dma_interconnect_1
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}
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2
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{
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set axi_dma_interconnect_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_dma_interconnect_2]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_dma_interconnect_2
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}
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3
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{
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set axi_dma_interconnect_3 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_dma_interconnect_3]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_dma_interconnect_3
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}
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}
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# connect the master port of the interconnect to the HP1, and connect aditional clock/reset signals
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connect_bd_net -net sys_100m_clk \
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[get_bd_pins sys_ps7/S_AXI_HP1_ACLK]
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connect_bd_net -net sys_100m_clk \
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[get_bd_pins axi_ddr_interconnect/M00_ACLK] $::sys_100m_clk_source
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[get_bd_pins "axi_dma_interconnect_${hp_port}/M00_ACLK"] $::sys_100m_clk_source
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connect_bd_net -net sys_100m_resetn \
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[get_bd_pins "axi_dma_interconnect_${hp_port}/M00_ARESETN"] $::sys_100m_resetn_source
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connect_bd_net -net sys_100m_clk \
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[get_bd_pins "axi_dma_interconnect_${hp_port}/ACLK"] $::sys_100m_clk_source
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connect_bd_net -net sys_100m_resetn \
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[get_bd_pins "axi_dma_interconnect_${hp_port}/ARESETN"] $::sys_100m_resetn_source
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connect_bd_intf_net -intf_net axi_ddr_interconnect_m00_axi \
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connect_bd_intf_net -intf_net axi_dma_interconnect_m00_axi \
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[get_bd_intf_pins "axi_dma_interconnect_${hp_port}/M00_AXI"] \
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[get_bd_intf_pins sys_ps7/S_AXI_HP1]
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# connect clk and reset for the interconnect
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connect_bd_net -net sys_200m_clk \
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[get_bd_pins "${axi_dma_interconnect_($hp_port)}/S00_ACLK"] \
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[get_bd_pins $clk]
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connect_bd_net -net sys_100m_resetn_intc \
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[get_bd_pins "$axi_dma_interconnect_($hp_port)/S00_ARESETN"] \
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[get_bd_pins $reset_i]
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connect_bd_net -net sys_100m_clk \
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[get_bd_pins "axi_dma_interconnect_${hp_port}/S00_ACLK"] \
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$::sys_100m_clk_source
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connect_bd_net -net sys_100m_resetn \
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[get_bd_pins "axi_dma_interconnect_${hp_port}/S00_ARESETN"] \
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$::sys_100m_resetn_source
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# connect clk and reset for the peripheral port
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puts "${dma_name}/${peripheral_port}_aclk"
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connect_bd_net -net sys_200m_clk \
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[get_bd_pins "${dma_name}/${peripheral_port}_aclk"]
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connect_bd_net -net sys_200m_resetn \
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[get_bd_pins "${dma_name}/${peripheral_port}_aresetn"]
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puts "${dma_name}/${port_name}_aclk"
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connect_bd_net -net sys_100m_clk \
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[get_bd_pins "${dma_name}/${port_name}_aclk"]
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connect_bd_net -net sys_100m_resetn \
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[get_bd_pins "${dma_name}/${port_name}_aresetn"]
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# Connect the interconnect to the dma
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connect_bd_intf_net -intf_net ${dma_name}_interconnect_s00_axi \
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connect_bd_intf_net -intf_net "axi_dma_interconnect_${hp_port}_s00_axi" \
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[get_bd_intf_pins "axi_dma_interconnect_${hp_port}/S00_AXI"] \
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[get_bd_intf_pins "${dma_name}/${port_name}"]
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@ -262,35 +288,34 @@ proc adi_dma_interconnect { dma_name port_name} {
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"SEG_sys_ps7_hp${hp_port}_ddr_lowocm"
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} else {
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set axi_ddr_interconnect [get_bd_cells axi_ddr_interconnect]
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set axi_mem_interconnect [get_bd_cells axi_mem_interconnect]
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# increment the number of the master ports of the interconnect
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set number_of_slave [get_property CONFIG.NUM_SI $axi_ddr_interconnect]
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set number_of_slave [get_property CONFIG.NUM_SI $axi_mem_interconnect]
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set number_of_slave [expr $number_of_slave + 1]
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set_property CONFIG.NUM_SI $number_of_slave $axi_ddr_interconnect
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set_property CONFIG.NUM_SI $number_of_slave $axi_mem_interconnect
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# connect clk and reset for the interconnect
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connect_bd_net -net sys_200m_clk \
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[get_bd_pins "${axi_ddr_interconnect}/S0[expr $number_of_slave-1]_ACLK"] \
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$::sys_200m_clk_source
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connect_bd_net -net sys_100m_resetn_intc \
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[get_bd_pins "$axi_ddr_interconnect/S0[expr $number_of_slave -1]_ARESETN"] \
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connect_bd_net -net sys_100m_clk \
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[get_bd_pins "${axi_mem_interconnect}/S0[expr $number_of_slave-1]_ACLK"] \
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$::sys_100m_clk_source
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connect_bd_net -net sys_100m_resetn \
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[get_bd_pins "$axi_mem_interconnect/S0[expr $number_of_slave -1]_ARESETN"] \
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$::sys_100m_resetn_source
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# connect clk and reset for the peripheral port
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puts "${dma_name}/${peripheral_port}_aclk"
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connect_bd_net -net sys_200m_clk \
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[get_bd_pins "${dma_name}/${peripheral_port}_aclk"]
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connect_bd_net -net sys_200m_resetn \
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[get_bd_pins "${dma_name}/${peripheral_port}_aresetn"]
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connect_bd_net -net sys_100m_clk \
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[get_bd_pins "${dma_name}/${port_name}_aclk"]
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connect_bd_net -net sys_100m_resetn \
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[get_bd_pins "${dma_name}/${port_name}_aresetn"]
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# make the port connection
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connect_bd_intf_net -intf_net "axi_ddr_interconnect_s${number_of_slave}" \
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[get_bd_intf_pins "$axi_ddr_interconnect/S0[expr $number_of_slave -1]_AXI"] \
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[get_bd_intf_pins "${dma_name}/${peripheral_port}"]
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connect_bd_intf_net -intf_net "axi_mem_interconnect_s${number_of_slave}" \
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[get_bd_intf_pins "$axi_mem_interconnect/S0[expr $number_of_slave -1]_AXI"] \
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[get_bd_intf_pins "${dma_name}/${port_name}"]
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# define address space for the peripheral
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create_bd_addr_seg -range $peripheral_address_range -offset $peripheral_address \
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[get_bd_addr_spaces "${dma_name}/${peripheral_port}"] \
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create_bd_addr_seg -range $::sys_mem_size -offset 0x00000000 \
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[get_bd_addr_spaces "${dma_name}/${port_name}"] \
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[get_bd_addr_segs "axi_ddr_cntrl/memmap/memaddr"] \
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"SEG_data_${dma_name}_2_ddr"
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}
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