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Add cn0506_rmii/zcu102 support on revB

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AndreiGrozav 2019-11-25 10:10:46 +02:00 committed by AndreiGrozav
parent 7e96514230
commit 8d6b8fc631
6 changed files with 324 additions and 0 deletions
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14
projects/cn0506_rmii/zcu102/Makefile Normal file
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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := cn0506_rmii_zcu102
M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
LIB_DEPS += axi_sysid
LIB_DEPS += sysid_rom
include ../../scripts/project-xilinx.mk

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projects/cn0506_rmii/zcu102/README.rst Normal file
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- Connect to FMC1
- Voltage 1.8V
- MII mode, using a MII-to-RMII converter. Connected to PS8's Ethernet 0(PHY 0) and Ethernet 1(PHY 1).

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projects/cn0506_rmii/zcu102/system_bd.tcl Normal file
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source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
# configuring one parameter at a time will end in a validation proces halt
set_property -dict [list \
CONFIG.PSU__ENET0__GRP_MDIO__ENABLE {1} \
CONFIG.PSU__ENET0__GRP_MDIO__IO {EMIO} \
CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__ENET0__PERIPHERAL__IO {EMIO} \
CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {1} \
CONFIG.PSU__ENET1__GRP_MDIO__IO {EMIO} \
CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__ENET1__PERIPHERAL__IO {EMIO} \
CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0}] [get_bd_cells sys_ps8]
create_bd_port -dir O reset_a
create_bd_port -dir O reset_b
create_bd_port -dir I ref_clk_50_a
create_bd_port -dir I ref_clk_50_b
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:rmii_rtl:1.0 RMII_PHY_M_0
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:rmii_rtl:1.0 RMII_PHY_M_1
make_bd_intf_pins_external [get_bd_intf_pins sys_ps8/MDIO_ENET0]
make_bd_intf_pins_external [get_bd_intf_pins sys_ps8/MDIO_ENET1]
ad_ip_instance mii_to_rmii mii_to_rmii_0
ad_ip_parameter mii_to_rmii_0 CONFIG.C_MODE 1
ad_ip_parameter mii_to_rmii_0 CONFIG.C_SPEED_100 1
ad_ip_parameter mii_to_rmii_0 CONFIG.C_FIXED_SPEED 0
ad_connect mii_to_rmii_0/GMII sys_ps8/GMII_ENET0
ad_connect mii_to_rmii_0/ref_clk ref_clk_50_a
ad_connect mii_to_rmii_0/RMII_PHY_M RMII_PHY_M_0
ad_ip_instance mii_to_rmii mii_to_rmii_1
ad_ip_parameter mii_to_rmii_1 CONFIG.C_MODE 1
ad_ip_parameter mii_to_rmii_1 CONFIG.C_SPEED_100 1
ad_ip_parameter mii_to_rmii_1 CONFIG.C_FIXED_SPEED 0
ad_connect mii_to_rmii_1/GMII sys_ps8/GMII_ENET1
ad_connect mii_to_rmii_1/ref_clk ref_clk_50_b
ad_connect mii_to_rmii_1/RMII_PHY_M RMII_PHY_M_1
ad_ip_instance proc_sys_reset proc_sys_reset_eth0
ad_connect proc_sys_reset_eth0/slowest_sync_clk ref_clk_50_a
ad_connect proc_sys_reset_eth0/ext_reset_in sys_rstgen/peripheral_aresetn
ad_connect proc_sys_reset_eth0/peripheral_reset reset_a
ad_connect proc_sys_reset_eth0/peripheral_aresetn mii_to_rmii_0/rst_n
ad_ip_instance proc_sys_reset proc_sys_reset_eth1
ad_connect proc_sys_reset_eth1/slowest_sync_clk ref_clk_50_b
ad_connect proc_sys_reset_eth1/ext_reset_in sys_rstgen/peripheral_aresetn
ad_connect proc_sys_reset_eth1/peripheral_reset reset_b
ad_connect proc_sys_reset_eth1/peripheral_aresetn mii_to_rmii_1/rst_n
#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
set sys_cstring "sys rom custom string placeholder"
sysid_gen_sys_init_file $sys_cstring

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projects/cn0506_rmii/zcu102/system_constr.xdc Normal file
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set_property -dict {PACKAGE_PIN AJ6 IOSTANDARD LVCMOS18} [get_ports rmii_rx_ref_clk_a] ; ## D08 FMC_HPC1_LA01_CC_P
set_property -dict {PACKAGE_PIN AJ5 IOSTANDARD LVCMOS18} [get_ports rmii_rx_er_a] ; ## D09 FMC_HPC1_LA01_CC_N
set_property -dict {PACKAGE_PIN AE4 IOSTANDARD LVCMOS18 PULLUP true} [get_ports rmii_rx_dv_a] ; ## H14 FMC_HPC1_LA07_N
set_property -dict {PACKAGE_PIN AE5 IOSTANDARD LVCMOS18 PULLUP true} [get_ports mac_if_sel_0_a] ; ## G06 FMC_HPC1_LA00_CC_P
set_property -dict {PACKAGE_PIN AD2 IOSTANDARD LVCMOS18} [get_ports {rmii_rxd_a[0]}] ; ## H07 FMC_HPC1_LA02_P
set_property -dict {PACKAGE_PIN AD1 IOSTANDARD LVCMOS18} [get_ports {rmii_rxd_a[1]}] ; ## H08 FMC_HPC1_LA02_N
set_property -dict {PACKAGE_PIN AD4 IOSTANDARD LVCMOS18 SLEW FAST} [get_ports rmii_tx_en_a] ; ## H13 FMC_HPC1_LA07_P
set_property -dict {PACKAGE_PIN AE2 IOSTANDARD LVCMOS18 SLEW FAST} [get_ports {rmii_txd_a[0]}] ; ## D14 FMC_HPC1_LA09_P
set_property -dict {PACKAGE_PIN AE1 IOSTANDARD LVCMOS18 SLEW FAST} [get_ports {rmii_txd_a[1]}] ; ## D15 FMC_HPC1_LA09_N
set_property -dict {PACKAGE_PIN AE8 IOSTANDARD LVCMOS18 PULLUP true} [get_ports mdio_fmc_a] ; ## H16 FMC_HPC1_LA11_P
set_property -dict {PACKAGE_PIN AF8 IOSTANDARD LVCMOS18} [get_ports mdc_fmc_a] ; ## H17 FMC_HPC1_LA11_N
set_property -dict {PACKAGE_PIN AD10 IOSTANDARD LVCMOS18} [get_ports reset_a] ; ## H19 FMC_HPC1_LA15_P
set_property -dict {PACKAGE_PIN AF2 IOSTANDARD LVCMOS18} [get_ports link_st_a] ; ## H10 FMC_HPC1_LA04_P
set_property -dict {PACKAGE_PIN AE3 IOSTANDARD LVCMOS18} [get_ports led_0_a] ; ## G12 FMC_HPC1_LA08_P
set_property -dict {PACKAGE_PIN AD7 IOSTANDARD LVCMOS18} [get_ports led_ar_c_c2m] ; ## G15 FMC_HPC1_LA12_P
set_property -dict {PACKAGE_PIN AD6 IOSTANDARD LVCMOS18} [get_ports led_ar_a_c2m] ; ## G16 FMC_HPC1_LA12_N
set_property -dict {PACKAGE_PIN AG8 IOSTANDARD LVCMOS18} [get_ports led_al_c_c2m] ; ## D17 FMC_HPC1_LA13_P
set_property -dict {PACKAGE_PIN AH8 IOSTANDARD LVCMOS18} [get_ports led_al_a_c2m] ; ## D18 FMC_HPC1_LA13_N
set_property -dict {PACKAGE_PIN Y5 IOSTANDARD LVCMOS18} [get_ports rmii_rx_ref_clk_b] ; ## D20 FMC_HPC1_LA17_CC_P
set_property -dict {PACKAGE_PIN AA5 IOSTANDARD LVCMOS18} [get_ports rmii_rx_er_b] ; ## D21 FMC_HPC1_LA17_CC_N
set_property -dict {PACKAGE_PIN AH11 IOSTANDARD LVCMOS18 PULLUP true} [get_ports rmii_rx_dv_b] ; ## H29 FMC_HPC1_LA24_N
set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS18 PULLUP true} [get_ports mac_if_sel_0_b] ; ## C22 FMC_HPC1_LA18_CC_P
set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVCMOS18} [get_ports {rmii_rxd_b[0]}] ; ## H22 FMC_HPC1_LA19_P
set_property -dict {PACKAGE_PIN AA10 IOSTANDARD LVCMOS18} [get_ports {rmii_rxd_b[1]}] ; ## H23 FMC_HPC1_LA19_N
set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS18 SLEW FAST} [get_ports rmii_tx_en_b] ; ## H28 FMC_HPC1_LA24_P
set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS18 SLEW FAST} [get_ports {rmii_txd_b[0]}] ; ## H25 FMC_HPC1_LA21_P
set_property -dict {PACKAGE_PIN AC11 IOSTANDARD LVCMOS18 SLEW FAST} [get_ports {rmii_txd_b[1]}] ; ## H26 FMC_HPC1_LA21_N
set_property -dict {PACKAGE_PIN T13 IOSTANDARD LVCMOS18 PULLUP true} [get_ports mdio_fmc_b] ; ## H31 FMC_HPC1_LA28_P
set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS18} [get_ports mdc_fmc_b] ; ## H32 FMC_HPC1_LA28_N
set_property -dict {PACKAGE_PIN AE9 IOSTANDARD LVCMOS18} [get_ports reset_b] ; ## H20 FMC_HPC1_LA15_N
set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS18} [get_ports link_st_b] ; ## G27 FMC_HPC1_LA25_P
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS18} [get_ports led_0_b] ; ## D23 FMC_HPC1_LA23_P
set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVCMOS18} [get_ports led_bl_c_c2m] ; ## D26 FMC_HPC1_LA26_P
set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS18} [get_ports led_bl_a_c2m] ; ## D27 FMC_HPC1_LA26_N
set_property -dict {PACKAGE_PIN AG10 IOSTANDARD LVCMOS18} [get_ports led_br_c_c2m] ; ## G18 FMC_HPC1_LA16_P
set_property -dict {PACKAGE_PIN AG9 IOSTANDARD LVCMOS18} [get_ports led_br_a_c2m] ; ## G19 FMC_HPC1_LA16_N
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets rmii_rx_ref_clk_a]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets rmii_rx_ref_clk_b]
create_clock -name rx_clk_a -period 20.0 [get_ports rmii_rx_ref_clk_a]
create_clock -name rx_clk_b -period 20.0 [get_ports rmii_rx_ref_clk_b]
create_clock -name mdio_clk_a -period 400.0 [get_pins i_system_wrapper/system_i/sys_ps8/inst/emio_enet0_mdio_mdc]
create_clock -name mdio_clk_b -period 400.0 [get_pins i_system_wrapper/system_i/sys_ps8/inst/emio_enet1_mdio_mdc]
create_clock -name mdio_0_rx_clk_a -period 40.0 [get_pins i_system_wrapper/system_i/sys_ps8/emio_enet0_gmii_rx_clk]
create_clock -name mdio_0_tx_clk_a -period 40.0 [get_pins i_system_wrapper/system_i/sys_ps8/emio_enet0_gmii_tx_clk]
create_clock -name mdio_0_rx_clk_b -period 40.0 [get_pins i_system_wrapper/system_i/sys_ps8/emio_enet1_gmii_rx_clk]
create_clock -name mdio_0_tx_clk_b -period 40.0 [get_pins i_system_wrapper/system_i/sys_ps8/emio_enet1_gmii_tx_clk]

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projects/cn0506_rmii/zcu102/system_project.tcl Normal file
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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project cn0506_rmii_zcu102
adi_project_files cn0506_rmii_zcu102 [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ]
adi_project_run cn0506_rmii_zcu102

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projects/cn0506_rmii/zcu102/system_top.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
input [12:0] gpio_bd_i,
output [ 7:0] gpio_bd_o,
// mii interface
output reset_a,
output mdc_fmc_a,
inout mdio_fmc_a,
input rmii_rx_ref_clk_a,
input [1:0] rmii_rxd_a,
input rmii_rx_dv_a,
input rmii_rx_er_a,
output [1:0] rmii_txd_a,
output rmii_tx_en_a,
input link_st_a,
input led_0_a,
output mac_if_sel_0_a,
output reset_b,
output mdc_fmc_b,
inout mdio_fmc_b,
input rmii_rx_ref_clk_b,
input [1:0] rmii_rxd_b,
input rmii_rx_dv_b,
input rmii_rx_er_b,
output [1:0] rmii_txd_b,
output rmii_tx_en_b,
input link_st_b,
input led_0_b,
output mac_if_sel_0_b,
// LEDs
output led_ar_c_c2m,
output led_ar_a_c2m,
output led_al_c_c2m,
output led_al_a_c2m,
output led_br_c_c2m,
output led_br_a_c2m,
output led_bl_c_c2m,
output led_bl_a_c2m
);
// internal signals
wire [94:0] gpio_i;
wire [94:0] gpio_o;
wire sys_reset_a;
wire sys_reset_b;
wire gpio_reset_a;
wire gpio_reset_b;
// assignments
assign mac_if_sel_0_a = 1'b1;
assign mac_if_sel_0_b = 1'b1;
// port a - right led (activity/status) yellow only
assign led_ar_c_c2m = led_0_a;
assign led_ar_a_c2m = 1'b0;
// port a - left led (speed mode): 10M=off, 100M=yellow
assign led_al_c_c2m = 1'b1;
assign led_al_a_c2m = 1'b0;
// port b - right led (activity/status) yellow only
assign led_br_c_c2m = led_0_b;
assign led_br_a_c2m = 1'b0;
// port a - left led (speed mode): 10M=off, 100M=yellow
assign led_bl_c_c2m = 1'b1;
assign led_bl_a_c2m = 1'b0;
assign gpio_i[94:36] = gpio_o[94:36];
assign gpio_reset_a = gpio_o[37];
assign gpio_reset_b = gpio_o[36];
assign reset_a = sys_reset_a | gpio_reset_a;
assign reset_b = sys_reset_b | gpio_reset_b;
assign gpio_i[35] = link_st_a;
assign gpio_i[34] = link_st_b;
assign gpio_i[33:21] = gpio_o[33:21];
assign gpio_i[20:8] = gpio_bd_i;
assign gpio_i[ 7:0] = gpio_o[7:0];
assign gpio_bd_o = gpio_o[ 7:0];
// instantiations
system_wrapper i_system_wrapper (
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (),
.spi0_csn (),
.spi0_miso (1'b0),
.spi0_mosi (),
.spi0_sclk (),
.spi1_csn (),
.spi1_miso (1'b0),
.spi1_mosi (),
.spi1_sclk (),
.reset_a (sys_reset_a),
.reset_b (sys_reset_b),
.ref_clk_50_a (rmii_rx_ref_clk_a),
.ref_clk_50_b (rmii_rx_ref_clk_b),
.MDIO_ENET0_0_mdc(mdc_fmc_a),
.MDIO_ENET0_0_mdio_io(mdio_fmc_a),
.RMII_PHY_M_0_crs_dv (rmii_rx_dv_a),
.RMII_PHY_M_0_rx_er (rmii_rx_er_a),
.RMII_PHY_M_0_rxd (rmii_rxd_a),
.RMII_PHY_M_0_tx_en (rmii_tx_en_a),
.RMII_PHY_M_0_txd (rmii_txd_a),
.MDIO_ENET1_0_mdc(mdc_fmc_b),
.MDIO_ENET1_0_mdio_io(mdio_fmc_b),
.RMII_PHY_M_1_crs_dv (rmii_rx_dv_b),
.RMII_PHY_M_1_rx_er (rmii_rx_er_b),
.RMII_PHY_M_1_rxd (rmii_rxd_b),
.RMII_PHY_M_1_tx_en (rmii_tx_en_b),
.RMII_PHY_M_1_txd (rmii_txd_b)
);
endmodule
// ***************************************************************************
// ***************************************************************************