jesd204_rx:jesd204_rx_ctrl_64b: Improve timing closure

library/jesd204/jesd204_rx/jesd204_rx_ctrl_64b.v

@@ -73,13 +73,22 @@ reg [1:0] state = STATE_RESET;
 reg [1:0] next_state;
 reg [5:0] good_cnt;
 reg rst_good_cnt;
+reg event_unexpected_lane_state_error_nx;
 
 wire [NUM_LANES-1:0] phy_block_sync_masked;
 wire [NUM_LANES-1:0] emb_lock_masked;
 wire all_block_sync;
 
+reg [NUM_LANES-1:0] emb_lock_d = {NUM_LANES{1'b0}};
+reg buffer_release_d_n = 1'b1;
+
+always @(posedge clk) begin
+  emb_lock_d <= emb_lock;
+  buffer_release_d_n <= buffer_release_n;
+end
+
 assign phy_block_sync_masked = phy_block_sync | cfg_lanes_disable;
-assign emb_lock_masked = emb_lock | cfg_lanes_disable;
+assign emb_lock_masked = emb_lock_d | cfg_lanes_disable;
 
 assign all_block_sync = &phy_block_sync_masked;
 assign all_emb_lock = &emb_lock_masked;
@@ -87,7 +96,7 @@ assign all_emb_lock = &emb_lock_masked;
 always @(*) begin
   next_state = state;
   rst_good_cnt = 1'b1;
-  event_unexpected_lane_state_error = 1'b0;
+  event_unexpected_lane_state_error_nx = 1'b0;
   case (state)
     STATE_RESET:
       next_state = STATE_WAIT_BS;
@@ -101,7 +110,7 @@ always @(*) begin
     STATE_BLOCK_SYNC:
       if (~all_block_sync) begin
         next_state = STATE_WAIT_BS;
-      end else if (all_emb_lock & ~buffer_release_n) begin
+      end else if (all_emb_lock & ~buffer_release_d_n) begin
         rst_good_cnt = 1'b0;
         if (&good_cnt) begin
           next_state = STATE_DATA;
@@ -110,10 +119,10 @@ always @(*) begin
     STATE_DATA:
       if (~all_block_sync) begin
         next_state = STATE_WAIT_BS;
-        event_unexpected_lane_state_error = 1'b1;
-      end else if (~all_emb_lock | buffer_release_n) begin
+        event_unexpected_lane_state_error_nx = 1'b1;
+      end else if (~all_emb_lock | buffer_release_d_n) begin
         next_state = STATE_BLOCK_SYNC;
-        event_unexpected_lane_state_error = 1'b1;
+        event_unexpected_lane_state_error_nx = 1'b1;
       end
   endcase
 end
@@ -135,6 +144,14 @@ always @(posedge clk) begin
   end
 end
 
+always @(posedge clk) begin
+  if (reset == 1'b1) begin
+    event_unexpected_lane_state_error <= 1'b0;
+  end else begin
+    event_unexpected_lane_state_error <= event_unexpected_lane_state_error_nx;
+  end
+end
+
 assign status_state = state;
 
 endmodule