util_axis_fifo: Switch data and tlast order, improve maintainability
parent
4a772265a9
commit
8ce1d6bf36
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@ -227,11 +227,11 @@ end else begin : fifo /* ADDRESS_WIDTH != 0 - this is a real FIFO implementation
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.clka(s_axis_aclk),
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.clka(s_axis_aclk),
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.wea(s_mem_write),
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.wea(s_mem_write),
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.addra(s_axis_waddr),
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.addra(s_axis_waddr),
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.dina({s_axis_data, s_axis_tlast}),
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.dina({s_axis_tlast, s_axis_data}),
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.clkb(m_axis_aclk),
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.clkb(m_axis_aclk),
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.reb(m_mem_read),
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.reb(m_mem_read),
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.addrb(m_axis_raddr),
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.addrb(m_axis_raddr),
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.doutb({m_axis_data, m_axis_tlast})
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.doutb({m_axis_tlast, m_axis_data})
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);
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);
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assign _m_axis_ready = ~valid || m_axis_ready;
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assign _m_axis_ready = ~valid || m_axis_ready;
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@ -245,7 +245,7 @@ end else begin : fifo /* ADDRESS_WIDTH != 0 - this is a real FIFO implementation
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// Let the synthesizer decide what to infer (distributed or block RAM)
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// Let the synthesizer decide what to infer (distributed or block RAM)
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always @(posedge s_axis_aclk) begin
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always @(posedge s_axis_aclk) begin
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if (s_mem_write)
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if (s_mem_write)
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ram[s_axis_waddr] <= {s_axis_data, s_axis_tlast};
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ram[s_axis_waddr] <= {s_axis_tlast, s_axis_data};
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end
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end
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if (M_AXIS_REGISTERED == 1) begin
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if (M_AXIS_REGISTERED == 1) begin
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@ -258,15 +258,15 @@ end else begin : fifo /* ADDRESS_WIDTH != 0 - this is a real FIFO implementation
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end
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end
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assign _m_axis_ready = ~valid || m_axis_ready;
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assign _m_axis_ready = ~valid || m_axis_ready;
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assign m_axis_data = data[DATA_WIDTH:1];
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assign m_axis_data = data[DATA_WIDTH-1:0];
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assign m_axis_tlast = data[0];
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assign m_axis_tlast = data[DATA_WIDTH];
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assign m_axis_valid = valid;
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assign m_axis_valid = valid;
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end else begin
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end else begin
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assign _m_axis_ready = m_axis_ready;
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assign _m_axis_ready = m_axis_ready;
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assign m_axis_valid = _m_axis_valid;
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assign m_axis_valid = _m_axis_valid;
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assign {m_axis_data, m_axis_tlast} = ram[m_axis_raddr];
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assign {m_axis_tlast, m_axis_data} = ram[m_axis_raddr];
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end
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end
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end
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end
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