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axi_ad9152: Updates for ad_dds phase acc wrapper

main
AndreiGrozav 2018-06-06 14:17:24 +03:00 committed by AndreiGrozav
parent a2d3c87aa5
commit 8cd88150f1
3 changed files with 10 additions and 0 deletions
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3
library/axi_ad9152/Makefile
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@ -18,7 +18,10 @@ ALTERA_DEPS += ../altera/common/up_xfer_cntrl_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_status_constr.sdc
ALTERA_DEPS += ../common/ad_dds.v
ALTERA_DEPS += ../common/ad_dds_1.v
ALTERA_DEPS += ../common/ad_dds_2.v
ALTERA_DEPS += ../common/ad_dds_cordic_pipe.v
ALTERA_DEPS += ../common/ad_dds_sine.v
ALTERA_DEPS += ../common/ad_dds_sine_cordic.v
ALTERA_DEPS += ../common/ad_rst.v
ALTERA_DEPS += ../common/up_axi.v
ALTERA_DEPS += ../common/up_clock_mon.v

4
library/axi_ad9152/axi_ad9152.v
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@ -40,6 +40,7 @@ module axi_ad9152 #(
parameter ID = 0,
parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
parameter DAC_DATAPATH_DISABLE = 0) (
// jesd interface
@ -91,6 +92,9 @@ module axi_ad9152 #(
.ID(ID),
.NUM_LANES(4),
.NUM_CHANNELS(2),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DAC_DATAPATH_DISABLE(DAC_DATAPATH_DISABLE)
) i_dac_jesd204 (
.link_clk (tx_clk),

3
library/axi_ad9152/axi_ad9152_hw.tcl
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@ -15,6 +15,9 @@ set_module_property DISPLAY_NAME axi_ad9152
ad_ip_files axi_ad9152 [list \
$ad_hdl_dir/library/altera/common/ad_mul.v \
$ad_hdl_dir/library/common/ad_dds_sine.v \
$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v \
$ad_hdl_dir/library/common/ad_dds_sine_cordic.v \
$ad_hdl_dir/library/common/ad_dds_2.v \
$ad_hdl_dir/library/common/ad_dds_1.v \
$ad_hdl_dir/library/common/ad_dds.v \
$ad_hdl_dir/library/common/ad_rst.v \