sidekiqz2: Initial commit
Adrian Costina
István Csomortáni
parent
9a44ab921b
commit
8c964389f6
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@ -41,6 +41,7 @@ all:
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-$(MAKE) -C m2k all
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-$(MAKE) -C motcon2_fmc all
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-$(MAKE) -C pluto all
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-$(MAKE) -C sidekiqz2 all
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-$(MAKE) -C usdrx1 all
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-$(MAKE) -C usrpe31x all
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@ -80,6 +81,7 @@ clean:
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$(MAKE) -C m2k clean
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$(MAKE) -C motcon2_fmc clean
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$(MAKE) -C pluto clean
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$(MAKE) -C sidekiqz2 clean
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$(MAKE) -C usdrx1 clean
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$(MAKE) -C usrpe31x clean
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@ -119,6 +121,7 @@ clean-all:
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$(MAKE) -C m2k clean-all
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$(MAKE) -C motcon2_fmc clean-all
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$(MAKE) -C pluto clean-all
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$(MAKE) -C sidekiqz2 clean-all
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$(MAKE) -C usdrx1 clean-all
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$(MAKE) -C usrpe31x clean-all
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@ -0,0 +1,67 @@
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####################################################################################
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####################################################################################
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## Copyright 2011(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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####################################################################################
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M_DEPS += system_top.v
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M_DEPS += system_project.tcl
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M_DEPS += system_constr.xdc
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M_DEPS += system_bd.tcl
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M_DEPS += ../scripts/adi_project.tcl
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M_DEPS += ../scripts/adi_env.tcl
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M_DEPS += ../scripts/adi_board.tcl
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M_DEPS += ../pluto/system_bd.tcl
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M_DEPS += ../../library/xilinx/common/ad_iobuf.v
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M_DEPS += ../../library/axi_ad9361/axi_ad9361.xpr
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M_DEPS += ../../library/axi_dmac/axi_dmac.xpr
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M_DEPS += ../../library/util_fir_dec/util_fir_dec.xpr
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M_DEPS += ../../library/util_fir_int/util_fir_int.xpr
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M_VIVADO := vivado -mode batch -source
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M_FLIST := *.cache
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M_FLIST += *.data
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M_FLIST += *.xpr
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M_FLIST += *.log
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M_FLIST += *.jou
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M_FLIST += xgui
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M_FLIST += *.runs
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M_FLIST += *.srcs
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M_FLIST += *.sdk
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M_FLIST += *.hw
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M_FLIST += *.sim
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M_FLIST += .Xil
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M_FLIST += *.ip_user_files
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.PHONY: all lib clean clean-all
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all: lib sidekiqz2.sdk/system_top.hdf
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clean:
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rm -rf $(M_FLIST)
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clean-all:clean
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$(MAKE) -C ../../library/axi_ad9361 clean
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$(MAKE) -C ../../library/axi_dmac clean
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$(MAKE) -C ../../library/util_fir_dec clean
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$(MAKE) -C ../../library/util_fir_int clean
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sidekiqz2.sdk/system_top.hdf: $(M_DEPS)
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-rm -rf $(M_FLIST)
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$(M_VIVADO) system_project.tcl >> sidekiqz2_vivado.log 2>&1
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lib:
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$(MAKE) -C ../../library/axi_ad9361
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$(MAKE) -C ../../library/axi_dmac
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$(MAKE) -C ../../library/util_fir_dec
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$(MAKE) -C ../../library/util_fir_int
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####################################################################################
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####################################################################################
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@ -0,0 +1,10 @@
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# create board design
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source ../pluto/system_bd.tcl
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ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_IO 19
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set_property LEFT 18 [get_bd_ports /gpio_i]
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set_property LEFT 18 [get_bd_ports /gpio_o]
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set_property LEFT 18 [get_bd_ports /gpio_t]
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@ -0,0 +1,72 @@
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# constraints
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# ad9361 (SWAP == 0x1)
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set_property -dict {PACKAGE_PIN N11 IOSTANDARD LVCMOS18 } [get_ports rx_clk_in]
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set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS18 } [get_ports rx_frame_in]
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set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[0]]
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set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[1]]
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set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[2]]
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set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[3]]
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set_property -dict {PACKAGE_PIN P13 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[4]]
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set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[5]]
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set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[6]]
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set_property -dict {PACKAGE_PIN R11 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[7]]
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set_property -dict {PACKAGE_PIN P10 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[8]]
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set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[9]]
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set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[10]]
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set_property -dict {PACKAGE_PIN P9 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[11]]
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set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports tx_clk_out]
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set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports tx_frame_out]
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set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports tx_data_out[0]]
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set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports tx_data_out[1]]
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set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports tx_data_out[2]]
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set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports tx_data_out[3]]
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set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports tx_data_out[4]]
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set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports tx_data_out[5]]
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set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports tx_data_out[6]]
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set_property -dict {PACKAGE_PIN M12 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports tx_data_out[7]]
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set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports tx_data_out[8]]
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set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports tx_data_out[9]]
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set_property -dict {PACKAGE_PIN M10 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports tx_data_out[10]]
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set_property -dict {PACKAGE_PIN M9 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports tx_data_out[11]]
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set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18} [get_ports gpio_status[0]]
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set_property -dict {PACKAGE_PIN G11 IOSTANDARD LVCMOS18} [get_ports gpio_status[1]]
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set_property -dict {PACKAGE_PIN G12 IOSTANDARD LVCMOS18} [get_ports gpio_status[2]]
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set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS18} [get_ports gpio_status[3]]
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set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS18} [get_ports gpio_status[4]]
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set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVCMOS18} [get_ports gpio_status[5]]
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set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports gpio_status[6]]
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set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports gpio_status[7]]
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set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]]
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set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]]
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set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]]
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set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]]
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set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc]
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set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS18} [get_ports enable]
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set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18} [get_ports txnrx]
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set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports iic_scl]
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set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports iic_sda]
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set_property -dict {PACKAGE_PIN P8 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports spi_csn]
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set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports spi_clk]
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set_property -dict {PACKAGE_PIN N7 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports spi_mosi]
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set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS18 OFFCHIP_TERM NONE} [get_ports spi_miso]
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set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18} [get_ports clk_out]
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create_clock -name rx_clk -period 16.27 [get_ports rx_clk_in]
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set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports pl_gpio[1]]
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set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS18} [get_ports pl_gpio[2]]
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set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS18} [get_ports pl_gpio[3]]
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set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS18} [get_ports pl_gpio[4]]
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set_false_path -from [get_pins {i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/up_adc_gpio_out_int_reg[0]*/C}]
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set_false_path -from [get_pins {i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/up_dac_gpio_out_int_reg[0]*/C}]
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@ -0,0 +1,15 @@
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source ../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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set p_device "xc7z010clg225-1"
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adi_project_xilinx sidekiqz2
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adi_project_files sidekiqz2 [list \
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"system_top.v" \
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"system_constr.xdc" \
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"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"]
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adi_project_run sidekiqz2
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@ -0,0 +1,168 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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inout [14:0] ddr_addr,
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inout [ 2:0] ddr_ba,
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inout ddr_cas_n,
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inout ddr_ck_n,
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inout ddr_ck_p,
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inout ddr_cke,
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inout ddr_cs_n,
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inout [ 1:0] ddr_dm,
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inout [15:0] ddr_dq,
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inout [ 1:0] ddr_dqs_n,
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inout [ 1:0] ddr_dqs_p,
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inout ddr_odt,
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inout ddr_ras_n,
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inout ddr_reset_n,
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inout ddr_we_n,
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inout fixed_io_ddr_vrn,
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inout fixed_io_ddr_vrp,
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inout [31:0] fixed_io_mio,
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inout fixed_io_ps_clk,
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inout fixed_io_ps_porb,
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inout fixed_io_ps_srstb,
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inout iic_scl,
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inout iic_sda,
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input rx_clk_in,
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input rx_frame_in,
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input [11:0] rx_data_in,
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output tx_clk_out,
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output tx_frame_out,
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output [11:0] tx_data_out,
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output enable,
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output txnrx,
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input clk_out,
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inout gpio_en_agc,
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inout [ 3:0] gpio_ctl,
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inout [ 7:0] gpio_status,
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inout [ 4:1] pl_gpio,
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output spi_csn,
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output spi_clk,
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output spi_mosi,
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input spi_miso);
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// internal signals
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wire [18:0] gpio_i;
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wire [18:0] gpio_o;
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wire [18:0] gpio_t;
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// instantiations
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ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
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.dio_t (gpio_t[16:0]),
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.dio_i (gpio_o[16:0]),
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.dio_o (gpio_i[16:0]),
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.dio_p ({ pl_gpio, // 16:13
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gpio_en_agc, // 12:12
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gpio_ctl, // 11: 8
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gpio_status})); // 7: 0
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system_wrapper i_system_wrapper (
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.ddr_addr (ddr_addr),
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.ddr_ba (ddr_ba),
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.ddr_cas_n (ddr_cas_n),
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.ddr_ck_n (ddr_ck_n),
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.ddr_ck_p (ddr_ck_p),
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.ddr_cke (ddr_cke),
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.ddr_cs_n (ddr_cs_n),
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.ddr_dm (ddr_dm),
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.ddr_dq (ddr_dq),
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.ddr_dqs_n (ddr_dqs_n),
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.ddr_dqs_p (ddr_dqs_p),
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.ddr_odt (ddr_odt),
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.ddr_ras_n (ddr_ras_n),
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.ddr_reset_n (ddr_reset_n),
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.ddr_we_n (ddr_we_n),
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.enable (enable),
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.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
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.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
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.fixed_io_mio (fixed_io_mio),
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.fixed_io_ps_clk (fixed_io_ps_clk),
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.fixed_io_ps_porb (fixed_io_ps_porb),
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.fixed_io_ps_srstb (fixed_io_ps_srstb),
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.ps_intr_00 (1'b0),
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.ps_intr_01 (1'b0),
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.ps_intr_02 (1'b0),
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.ps_intr_03 (1'b0),
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.ps_intr_04 (1'b0),
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.ps_intr_05 (1'b0),
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.ps_intr_06 (1'b0),
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.ps_intr_07 (1'b0),
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.ps_intr_08 (1'b0),
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.ps_intr_09 (1'b0),
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.ps_intr_10 (1'b0),
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.ps_intr_11 (1'b0),
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.ps_intr_14 (1'b0),
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.rx_clk_in (rx_clk_in),
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.rx_data_in (rx_data_in),
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.rx_frame_in (rx_frame_in),
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.spi0_clk_i (1'b0),
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.spi0_clk_o (spi_clk),
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.spi0_csn_0_o (spi_csn),
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.spi0_csn_1_o (),
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.spi0_csn_2_o (),
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.spi0_csn_i (1'b1),
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.spi0_sdi_i (spi_miso),
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.spi0_sdo_i (1'b0),
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.spi0_sdo_o (spi_mosi),
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.tx_clk_out (tx_clk_out),
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.tx_data_out (tx_data_out),
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.tx_frame_out (tx_frame_out),
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.txnrx (txnrx),
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.up_enable (gpio_o[17]),
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.up_txnrx (gpio_o[18]));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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