pzsdr1- common files
Rejeesh Kutty
parent
4dae754287
commit
8c25402d53
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@ -0,0 +1,427 @@
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# create board design
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# default ports
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main
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create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io
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create_bd_port -dir O spi0_csn_2_o
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create_bd_port -dir O spi0_csn_1_o
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create_bd_port -dir O spi0_csn_0_o
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create_bd_port -dir I spi0_csn_i
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create_bd_port -dir I spi0_clk_i
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create_bd_port -dir O spi0_clk_o
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create_bd_port -dir I spi0_sdo_i
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create_bd_port -dir O spi0_sdo_o
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create_bd_port -dir I spi0_sdi_i
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create_bd_port -dir O spi1_csn_2_o
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create_bd_port -dir O spi1_csn_1_o
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create_bd_port -dir O spi1_csn_0_o
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create_bd_port -dir I spi1_csn_i
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create_bd_port -dir I spi1_clk_i
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create_bd_port -dir O spi1_clk_o
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create_bd_port -dir I spi1_sdo_i
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create_bd_port -dir O spi1_sdo_o
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create_bd_port -dir I spi1_sdi_i
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create_bd_port -dir I -from 63 -to 0 gpio_i
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create_bd_port -dir O -from 63 -to 0 gpio_o
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create_bd_port -dir O -from 63 -to 0 gpio_t
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# otg
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set otg_vbusoc [create_bd_port -dir I otg_vbusoc]
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# interrupts
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create_bd_port -dir I -type intr ps_intr_00
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create_bd_port -dir I -type intr ps_intr_01
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create_bd_port -dir I -type intr ps_intr_02
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create_bd_port -dir I -type intr ps_intr_03
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create_bd_port -dir I -type intr ps_intr_04
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create_bd_port -dir I -type intr ps_intr_05
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create_bd_port -dir I -type intr ps_intr_06
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create_bd_port -dir I -type intr ps_intr_07
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create_bd_port -dir I -type intr ps_intr_08
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create_bd_port -dir I -type intr ps_intr_09
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create_bd_port -dir I -type intr ps_intr_10
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create_bd_port -dir I -type intr ps_intr_11
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create_bd_port -dir I -type intr ps_intr_12
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create_bd_port -dir I -type intr ps_intr_13
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create_bd_port -dir I -type intr ps_intr_15
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# instance: sys_ps7
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set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7]
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set_property -dict [list CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V}] $sys_ps7
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set_property -dict [list CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V}] $sys_ps7
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set_property -dict [list CONFIG.PCW_PACKAGE_NAME {fbg676}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27}] $sys_ps7
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set_property -dict [list CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_ENET_RESET_SELECT {Separate reset pins}] $sys_ps7
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set_property -dict [list CONFIG.PCW_ENET0_RESET_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_ENET0_RESET_IO {MIO 8}] $sys_ps7
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set_property -dict [list CONFIG.PCW_ENET1_RESET_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_ENET1_RESET_IO {MIO 51}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SD0_GRP_CD_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SD0_GRP_CD_IO {MIO 50}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USB0_RESET_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USB0_RESET_IO {MIO 7}] $sys_ps7
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set_property -dict [list CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.110}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.095}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.249}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.249}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.202}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.217}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.216}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.217}] $sys_ps7
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set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7
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set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7
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set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
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set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_iic_main
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set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_main
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set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
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set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
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set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
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set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen
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set sys_logic_inv [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 sys_logic_inv]
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set_property -dict [list CONFIG.C_SIZE {1}] $sys_logic_inv
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set_property -dict [list CONFIG.C_OPERATION {not}] $sys_logic_inv
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# system reset/clock definitions
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ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0
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ad_connect sys_200m_clk sys_ps7/FCLK_CLK1
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ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
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ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
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ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
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ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
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# interface connections
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ad_connect ddr sys_ps7/DDR
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ad_connect gpio_i sys_ps7/GPIO_I
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ad_connect gpio_o sys_ps7/GPIO_O
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ad_connect gpio_t sys_ps7/GPIO_T
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ad_connect fixed_io sys_ps7/FIXED_IO
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ad_connect iic_main axi_iic_main/iic
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ad_connect sys_logic_inv/Res sys_ps7/USB0_VBUS_PWRFAULT
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ad_connect sys_logic_inv/Op1 otg_vbusoc
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# spi connections
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ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O
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ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O
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ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O
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ad_connect spi0_csn_i sys_ps7/SPI0_SS_I
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ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I
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ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O
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ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I
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ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O
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ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I
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ad_connect spi1_csn_2_o sys_ps7/SPI1_SS2_O
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ad_connect spi1_csn_1_o sys_ps7/SPI1_SS1_O
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ad_connect spi1_csn_0_o sys_ps7/SPI1_SS_O
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ad_connect spi1_csn_i sys_ps7/SPI1_SS_I
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ad_connect spi1_clk_i sys_ps7/SPI1_SCLK_I
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ad_connect spi1_clk_o sys_ps7/SPI1_SCLK_O
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ad_connect spi1_sdo_i sys_ps7/SPI1_MOSI_I
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ad_connect spi1_sdo_o sys_ps7/SPI1_MOSI_O
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ad_connect spi1_sdi_i sys_ps7/SPI1_MISO_I
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# interrupts
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ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P
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ad_connect sys_concat_intc/In15 ps_intr_15
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ad_connect sys_concat_intc/In14 axi_iic_main/iic2intc_irpt
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ad_connect sys_concat_intc/In13 ps_intr_13
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ad_connect sys_concat_intc/In12 ps_intr_12
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ad_connect sys_concat_intc/In11 ps_intr_11
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ad_connect sys_concat_intc/In10 ps_intr_10
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ad_connect sys_concat_intc/In9 ps_intr_09
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ad_connect sys_concat_intc/In8 ps_intr_08
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ad_connect sys_concat_intc/In7 ps_intr_07
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ad_connect sys_concat_intc/In6 ps_intr_06
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ad_connect sys_concat_intc/In5 ps_intr_05
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ad_connect sys_concat_intc/In4 ps_intr_04
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ad_connect sys_concat_intc/In3 ps_intr_03
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ad_connect sys_concat_intc/In2 ps_intr_02
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ad_connect sys_concat_intc/In1 ps_intr_01
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ad_connect sys_concat_intc/In0 ps_intr_00
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# interconnects
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ad_cpu_interconnect 0x41600000 axi_iic_main
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# ad9361
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create_bd_port -dir O enable
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create_bd_port -dir O txnrx
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create_bd_port -dir I up_enable
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create_bd_port -dir I up_txnrx
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create_bd_port -dir O tdd_sync_o
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create_bd_port -dir I tdd_sync_i
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create_bd_port -dir O tdd_sync_t
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# ad9361 core
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set axi_ad9361 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361]
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set_property -dict [list CONFIG.ID {0}] $axi_ad9361
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set_property -dict [list CONFIG.DAC_IODELAY_ENABLE {0}] $axi_ad9361
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set axi_ad9361_dac_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_dac_dma]
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set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9361_dac_dma
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set util_ad9361_dac_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_ad9361_dac_upack]
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9361_dac_upack
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9361_dac_upack
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set axi_ad9361_adc_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_adc_dma]
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set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9361_adc_dma
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set util_ad9361_adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9361_adc_pack]
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9361_adc_pack
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9361_adc_pack
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set util_ad9361_adc_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_wfifo:1.0 util_ad9361_adc_fifo]
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9361_adc_fifo
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set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $util_ad9361_adc_fifo
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set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $util_ad9361_adc_fifo
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set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $util_ad9361_adc_fifo
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set util_ad9361_tdd_sync [create_bd_cell -type ip -vlnv analog.com:user:util_tdd_sync:1.0 util_ad9361_tdd_sync]
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set_property -dict [list CONFIG.TDD_SYNC_PERIOD {10000000}] $util_ad9361_tdd_sync
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# connections
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ad_connect sys_200m_clk axi_ad9361/delay_clk
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ad_connect axi_ad9361_clk axi_ad9361/l_clk
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ad_connect axi_ad9361_clk axi_ad9361/clk
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ad_connect enable axi_ad9361/enable
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ad_connect txnrx axi_ad9361/txnrx
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ad_connect up_enable axi_ad9361/up_enable
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ad_connect up_txnrx axi_ad9361/up_txnrx
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ad_connect axi_ad9361_clk util_ad9361_adc_fifo/din_clk
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ad_connect axi_ad9361/rst util_ad9361_adc_fifo/din_rst
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ad_connect sys_cpu_clk util_ad9361_adc_fifo/dout_clk
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ad_connect sys_cpu_resetn util_ad9361_adc_fifo/dout_rstn
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ad_connect sys_cpu_clk util_ad9361_adc_pack/adc_clk
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ad_connect sys_cpu_reset util_ad9361_adc_pack/adc_rst
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ad_connect sys_cpu_clk axi_ad9361_adc_dma/fifo_wr_clk
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ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0
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ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0
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ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0
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ad_connect axi_ad9361/adc_enable_q0 util_ad9361_adc_fifo/din_enable_1
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ad_connect axi_ad9361/adc_valid_q0 util_ad9361_adc_fifo/din_valid_1
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ad_connect axi_ad9361/adc_data_q0 util_ad9361_adc_fifo/din_data_1
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ad_connect axi_ad9361/adc_enable_i1 util_ad9361_adc_fifo/din_enable_2
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ad_connect axi_ad9361/adc_valid_i1 util_ad9361_adc_fifo/din_valid_2
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ad_connect axi_ad9361/adc_data_i1 util_ad9361_adc_fifo/din_data_2
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ad_connect axi_ad9361/adc_enable_q1 util_ad9361_adc_fifo/din_enable_3
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ad_connect axi_ad9361/adc_valid_q1 util_ad9361_adc_fifo/din_valid_3
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ad_connect axi_ad9361/adc_data_q1 util_ad9361_adc_fifo/din_data_3
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ad_connect util_ad9361_adc_fifo/dout_enable_0 util_ad9361_adc_pack/adc_enable_0
|
||||
ad_connect util_ad9361_adc_fifo/dout_valid_0 util_ad9361_adc_pack/adc_valid_0
|
||||
ad_connect util_ad9361_adc_fifo/dout_data_0 util_ad9361_adc_pack/adc_data_0
|
||||
ad_connect util_ad9361_adc_fifo/dout_enable_1 util_ad9361_adc_pack/adc_enable_1
|
||||
ad_connect util_ad9361_adc_fifo/dout_valid_1 util_ad9361_adc_pack/adc_valid_1
|
||||
ad_connect util_ad9361_adc_fifo/dout_data_1 util_ad9361_adc_pack/adc_data_1
|
||||
ad_connect util_ad9361_adc_fifo/dout_enable_2 util_ad9361_adc_pack/adc_enable_2
|
||||
ad_connect util_ad9361_adc_fifo/dout_valid_2 util_ad9361_adc_pack/adc_valid_2
|
||||
ad_connect util_ad9361_adc_fifo/dout_data_2 util_ad9361_adc_pack/adc_data_2
|
||||
ad_connect util_ad9361_adc_fifo/dout_enable_3 util_ad9361_adc_pack/adc_enable_3
|
||||
ad_connect util_ad9361_adc_fifo/dout_valid_3 util_ad9361_adc_pack/adc_valid_3
|
||||
ad_connect util_ad9361_adc_fifo/dout_data_3 util_ad9361_adc_pack/adc_data_3
|
||||
ad_connect util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en
|
||||
ad_connect util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync
|
||||
ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din
|
||||
ad_connect axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf
|
||||
ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf
|
||||
ad_connect axi_ad9361_clk util_ad9361_dac_upack/dac_clk
|
||||
ad_connect axi_ad9361_clk axi_ad9361_dac_dma/fifo_rd_clk
|
||||
ad_connect util_ad9361_dac_upack/dac_enable_0 axi_ad9361/dac_enable_i0
|
||||
ad_connect util_ad9361_dac_upack/dac_valid_0 axi_ad9361/dac_valid_i0
|
||||
ad_connect util_ad9361_dac_upack/dac_data_0 axi_ad9361/dac_data_i0
|
||||
ad_connect util_ad9361_dac_upack/dac_enable_1 axi_ad9361/dac_enable_q0
|
||||
ad_connect util_ad9361_dac_upack/dac_valid_1 axi_ad9361/dac_valid_q0
|
||||
ad_connect util_ad9361_dac_upack/dac_data_1 axi_ad9361/dac_data_q0
|
||||
ad_connect util_ad9361_dac_upack/dac_enable_2 axi_ad9361/dac_enable_i1
|
||||
ad_connect util_ad9361_dac_upack/dac_valid_2 axi_ad9361/dac_valid_i1
|
||||
ad_connect util_ad9361_dac_upack/dac_data_2 axi_ad9361/dac_data_i1
|
||||
ad_connect util_ad9361_dac_upack/dac_enable_3 axi_ad9361/dac_enable_q1
|
||||
ad_connect util_ad9361_dac_upack/dac_valid_3 axi_ad9361/dac_valid_q1
|
||||
ad_connect util_ad9361_dac_upack/dac_data_3 axi_ad9361/dac_data_q1
|
||||
ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en
|
||||
ad_connect util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout
|
||||
ad_connect axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf
|
||||
ad_connect sys_cpu_clk util_ad9361_tdd_sync/clk
|
||||
ad_connect sys_cpu_resetn util_ad9361_tdd_sync/rstn
|
||||
ad_connect util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync
|
||||
ad_connect util_ad9361_tdd_sync/sync_mode axi_ad9361/tdd_sync_cntr
|
||||
ad_connect tdd_sync_t axi_ad9361/tdd_sync_cntr
|
||||
ad_connect tdd_sync_o util_ad9361_tdd_sync/sync_out
|
||||
ad_connect tdd_sync_i util_ad9361_tdd_sync/sync_in
|
||||
|
||||
# interconnects
|
||||
|
||||
ad_cpu_interconnect 0x79020000 axi_ad9361
|
||||
ad_cpu_interconnect 0x7C400000 axi_ad9361_adc_dma
|
||||
ad_cpu_interconnect 0x7C420000 axi_ad9361_dac_dma
|
||||
ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
|
||||
ad_mem_hp1_interconnect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi
|
||||
ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
|
||||
ad_mem_hp2_interconnect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi
|
||||
ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn
|
||||
ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn
|
||||
|
||||
# interrupts
|
||||
|
||||
ad_cpu_interrupt ps-13 mb-13 axi_ad9361_adc_dma/irq
|
||||
ad_cpu_interrupt ps-12 mb-12 axi_ad9361_dac_dma/irq
|
||||
|
||||
## customization of core to disable data path logic (less resources)
|
||||
## interface type - 1R1T (1) or 2R2T (0) (default is 2R2T)
|
||||
## 2R2T supports 1R1T as a run time option.
|
||||
## 1R1T allows core to run at a lower rate (1/2 of 2R2T)
|
||||
|
||||
set_property CONFIG.MODE_1R1T 0 [get_bd_cells axi_ad9361]
|
||||
|
||||
## interface type - CMOS (1) or LVDS (0) (default is LVDS)
|
||||
## CMOS allows core to run at a lower rate (1/2 of LVDS)
|
||||
|
||||
set_property CONFIG.CMOS_OR_LVDS_N 0 [get_bd_cells axi_ad9361]
|
||||
|
||||
## data-path disable (global control)- allows removal of DSP functions within the core.
|
||||
## also removes the corresponding AXI control interface registers
|
||||
|
||||
set_property CONFIG.ADC_DATAPATH_DISABLE 0 [get_bd_cells axi_ad9361]
|
||||
set_property CONFIG.DAC_DATAPATH_DISABLE 0 [get_bd_cells axi_ad9361]
|
||||
|
||||
## data-path disable (individual control)- effective ONLY if DATAPATH_DISABLE is 0x0.
|
||||
|
||||
set_property CONFIG.ADC_DATAFORMAT_DISABLE 0 [get_bd_cells axi_ad9361]
|
||||
set_property CONFIG.ADC_DCFILTER_DISABLE 0 [get_bd_cells axi_ad9361]
|
||||
set_property CONFIG.ADC_IQCORRECTION_DISABLE 0 [get_bd_cells axi_ad9361]
|
||||
set_property CONFIG.ADC_USERPORTS_DISABLE 0 [get_bd_cells axi_ad9361]
|
||||
|
||||
set_property CONFIG.DAC_DDS_DISABLE 0 [get_bd_cells axi_ad9361]
|
||||
set_property CONFIG.DAC_IQCORRECTION_DISABLE 0 [get_bd_cells axi_ad9361]
|
||||
set_property CONFIG.DAC_USERPORTS_DISABLE 0 [get_bd_cells axi_ad9361]
|
||||
|
||||
## tdd-disable (control is moved exclusively to GPIO)
|
||||
|
||||
set_property CONFIG.TDD_DISABLE 0 [get_bd_cells axi_ad9361]
|
||||
|
||||
## lvds/cmos configuration
|
||||
## core digital interface -- cmos (1) or lvds (0)
|
||||
|
||||
proc cfg_ad9361_interface {cmos_or_lvds} {
|
||||
|
||||
if {$cmos_or_lvds eq "LVDS"} {
|
||||
|
||||
set_property CONFIG.CMOS_OR_LVDS_N 0 [get_bd_cells axi_ad9361]
|
||||
|
||||
create_bd_port -dir I rx_clk_in_p
|
||||
create_bd_port -dir I rx_clk_in_n
|
||||
create_bd_port -dir I rx_frame_in_p
|
||||
create_bd_port -dir I rx_frame_in_n
|
||||
create_bd_port -dir I -from 5 -to 0 rx_data_in_p
|
||||
create_bd_port -dir I -from 5 -to 0 rx_data_in_n
|
||||
|
||||
create_bd_port -dir O tx_clk_out_p
|
||||
create_bd_port -dir O tx_clk_out_n
|
||||
create_bd_port -dir O tx_frame_out_p
|
||||
create_bd_port -dir O tx_frame_out_n
|
||||
create_bd_port -dir O -from 5 -to 0 tx_data_out_p
|
||||
create_bd_port -dir O -from 5 -to 0 tx_data_out_n
|
||||
|
||||
ad_connect rx_clk_in_p axi_ad9361/rx_clk_in_p
|
||||
ad_connect rx_clk_in_n axi_ad9361/rx_clk_in_n
|
||||
ad_connect rx_frame_in_p axi_ad9361/rx_frame_in_p
|
||||
ad_connect rx_frame_in_n axi_ad9361/rx_frame_in_n
|
||||
ad_connect rx_data_in_p axi_ad9361/rx_data_in_p
|
||||
ad_connect rx_data_in_n axi_ad9361/rx_data_in_n
|
||||
ad_connect tx_clk_out_p axi_ad9361/tx_clk_out_p
|
||||
ad_connect tx_clk_out_n axi_ad9361/tx_clk_out_n
|
||||
ad_connect tx_frame_out_p axi_ad9361/tx_frame_out_p
|
||||
ad_connect tx_frame_out_n axi_ad9361/tx_frame_out_n
|
||||
ad_connect tx_data_out_p axi_ad9361/tx_data_out_p
|
||||
ad_connect tx_data_out_n axi_ad9361/tx_data_out_n
|
||||
|
||||
return
|
||||
}
|
||||
|
||||
if {$cmos_or_lvds eq "CMOS"} {
|
||||
|
||||
set_property CONFIG.CMOS_OR_LVDS_N 1 [get_bd_cells axi_ad9361]
|
||||
|
||||
create_bd_port -dir I rx_clk_in
|
||||
create_bd_port -dir I rx_frame_in
|
||||
create_bd_port -dir I -from 11 -to 0 rx_data_in
|
||||
create_bd_port -dir O tx_clk_out
|
||||
create_bd_port -dir O tx_frame_out
|
||||
create_bd_port -dir O -from 11 -to 0 tx_data_out
|
||||
|
||||
ad_connect rx_clk_in axi_ad9361/rx_clk_in
|
||||
ad_connect rx_frame_in axi_ad9361/rx_frame_in
|
||||
ad_connect rx_data_in axi_ad9361/rx_data_in
|
||||
ad_connect tx_clk_out axi_ad9361/tx_clk_out
|
||||
ad_connect tx_frame_out axi_ad9361/tx_frame_out
|
||||
ad_connect tx_data_out axi_ad9361/tx_data_out
|
||||
|
||||
return
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,188 @@
|
|||
|
||||
# constraints (pzsdr1.b)
|
||||
# ad9361
|
||||
|
||||
set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS25} [get_ports enable] ; ## IO_L11P_T1_SRCC_35 U1,L16,IO_L11_35_ENABLE
|
||||
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## IO_L11N_T1_SRCC_35 U1,L17,IO_L11_35_TXNRX
|
||||
|
||||
set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS25} [get_ports gpio_status[0]] ; ## IO_L19P_T3_35 U1,H15,IO_L19_35_CTRL_OUT0
|
||||
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS25} [get_ports gpio_status[1]] ; ## IO_L19N_T3_VREF_35 U1,G15,IO_L19_35_CTRL_OUT1
|
||||
set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVCMOS25} [get_ports gpio_status[2]] ; ## IO_L20P_T3_AD6P_35 U1,K14,IO_L20_35_CTRL_OUT2
|
||||
set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS25} [get_ports gpio_status[3]] ; ## IO_L20N_T3_AD6N_35 U1,J14,IO_L20_35_CTRL_OUT3
|
||||
set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS25} [get_ports gpio_status[4]] ; ## IO_L21P_T3_DQS_AD14P_35 U1,N15,IO_L21_35_CTRL_OUT4
|
||||
set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS25} [get_ports gpio_status[5]] ; ## IO_L21N_T3_DQS_AD14N_35 U1,N16,IO_L21_35_CTRL_OUT5
|
||||
set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS25} [get_ports gpio_status[6]] ; ## IO_L22P_T3_AD7P_35 U1,L14,IO_L22_35_CTRL_OUT6
|
||||
set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS25} [get_ports gpio_status[7]] ; ## IO_L22N_T3_AD7N_35 U1,L15,IO_L22_35_CTRL_OUT7
|
||||
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[0]] ; ## IO_L23P_T3_34 U1,N17,IO_L23_34_CTRL_IN0
|
||||
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[1]] ; ## IO_L23N_T3_34 U1,P18,IO_L23_34_CTRL_IN1
|
||||
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[2]] ; ## IO_L24P_T3_34 U1,P15,IO_L24_34_CTRL_IN2
|
||||
set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[3]] ; ## IO_L24N_T3_34 U1,P16,IO_L24_34_CTRL_IN3
|
||||
set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## IO_L10P_T1_AD11P_35 U1,K19,IO_L10_35_EN_AGC
|
||||
set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## IO_L10N_T1_AD11N_35 U1,J19,IO_L10_35_SYNC_IN
|
||||
set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## IO_0_35 U1,G14,IO_00_35_AD9364_RST
|
||||
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports gpio_clksel] ; ## IO_0_34 U1,R19,IO_00_34_AD9364_CLKSEL
|
||||
|
||||
set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn] ; ## IO_L23P_T3_35 U1,M14,IO_L23_35_SPI_ENB
|
||||
set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## IO_L23N_T3_35 U1,M15,IO_L23_35_SPI_CLK
|
||||
set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## IO_L24P_T3_AD15P_35 U1,K16,IO_L24_35_SPI_DI
|
||||
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## IO_L24N_T3_AD15N_35 U1,J16,IO_L24_35_SPI_DO
|
||||
|
||||
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS25} [get_ports clkout_in] ; ## IO_25_35 U1,J15,IO_25_35_AD9364_CLKOUT
|
||||
|
||||
# iic
|
||||
|
||||
set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl] ; ## IO_L22N_T3_13 U1,W6,SCL,JX2,17,I2C_SCL
|
||||
set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda] ; ## IO_L22P_T3_13 U1,V6,SDA,JX2,19,I2C_SDA
|
||||
|
||||
## reference-only
|
||||
## --------------
|
||||
## ad9361 (optional rf-card)
|
||||
## --------------------------
|
||||
## JX4,1,GPO0
|
||||
## JX4,2,GPO1
|
||||
## JX4,3,GPO2
|
||||
## JX4,4,GPO3
|
||||
## JX4,7,AUXADC
|
||||
## JX4,8,AUXDAC1
|
||||
## JX4,10,AUXDAC2
|
||||
## JX4,63,AD9364_CLK
|
||||
|
||||
## fixed-io (ps7) (som only, others are carrier specific)
|
||||
## ------------------------------------------------------
|
||||
## U1,A7,PS_MIO01_500_QSPI0_SS_B
|
||||
## U1,A5,PS_MIO06_500_QSPI0_SCLK
|
||||
## U1,B8,PS_MIO02_500_QSPI0_IO0
|
||||
## U1,D6,PS_MIO03_500_QSPI0_IO1
|
||||
## U1,B7,PS_MIO04_500_QSPI0_IO2
|
||||
## U1,A6,PS_MIO05_500_QSPI0_IO3
|
||||
## U1,D5,PS_MIO08_500_ETH0_RESETN (magnetics-RJ45- JX3,47,ETH_PHY_LED0)
|
||||
## U1,C11,PS_MIO53_501_ETH0_MDIO (magnetics-RJ45- JX3,48,ETH_PHY_LED1)
|
||||
## U1,C10,PS_MIO52_501_ETH0_MDC (magnetics-RJ45- JX3,51,ETH_MD1_P)
|
||||
## U1,B17,PS_MIO22_501_ETH0_RX_CLK (magnetics-RJ45- JX3,53,ETH_MD1_N)
|
||||
## U1,D13,PS_MIO27_501_ETH0_RX_CTL (magnetics-RJ45- JX3,52,ETH_MD2_P)
|
||||
## U1,D11,PS_MIO23_501_ETH0_RX_D0 (magnetics-RJ45- JX3,54,ETH_MD2_N)
|
||||
## U1,A16,PS_MIO24_501_ETH0_RX_D1 (magnetics-RJ45- JX3,57,ETH_MD3_P)
|
||||
## U1,F15,PS_MIO25_501_ETH0_RX_D2 (magnetics-RJ45- JX3,59,ETH_MD3_P)
|
||||
## U1,A15,PS_MIO26_501_ETH0_RX_D3 (magnetics-RJ45- JX3,58,ETH_MD4_P)
|
||||
## U1,A19,PS_MIO16_501_ETH0_TX_CLK (magnetics-RJ45- JX3,60,ETH_MD4_P)
|
||||
## U1,F14,PS_MIO21_501_ETH0_TX_CTL
|
||||
## U1,E14,PS_MIO17_501_ETH0_TX_D0
|
||||
## U1,B18,PS_MIO18_501_ETH0_TX_D1
|
||||
## U1,D10,PS_MIO19_501_ETH0_TX_D2
|
||||
## U1,A17,PS_MIO20_501_ETH0_TX_D3
|
||||
## U1,B12,PS_MIO48_501_JX4,JX4,99,USB_UART_RXD
|
||||
## U1,C12,PS_MIO49_501_JX4,JX4,98,USB_UART_TXD
|
||||
## U1,D14,PS_MIO40_501_SD0_CLK (off-board- JX3,43,SDIO_CLKB1)
|
||||
## U1,C17,PS_MIO41_501_SD0_CMD (off-board- JX3,34,SDIO_CMDB1)
|
||||
## U1,E12,PS_MIO42_501_SD0_DATA0 (off-board- JX3,37,SDIO_DAT0B1)
|
||||
## U1,A9,PS_MIO43_501_SD0_DATA1 (off-board- JX3,36,SDIO_DAT1B1)
|
||||
## U1,F13,PS_MIO44_501_SD0_DATA2 (off-board- JX3,39,SDIO_DAT2B1)
|
||||
## U1,B15,PS_MIO45_501_SD0_DATA3 (off-board- JX3,38,SDIO_DAT3B1)
|
||||
## U1,B13,PS_MIO50_501_SD0_CD (off-board- JX3,41,JX3_SD1_CDN)
|
||||
## U1,D8,PS_MIO07_500_USB_RESET_B (usb- JX3,63,USB_ID)
|
||||
## U1,B5,PS_MIO09_500_USB_CLK_PD (usb- JX3,67,USB_OTG_P)
|
||||
## U1,C13,PS_MIO29_501_USB0_DIR (usb- JX3,69,USB_OTG_N)
|
||||
## U1,C15,PS_MIO30_501_USB0_STP (usb- JX3,68,USB_VBUS_OTG)
|
||||
## U1,E16,PS_MIO31_501_USB0_NXT (usb- JX3,70,USB_OTG_CPEN)
|
||||
## U1,A11,PS_MIO36_501_USB0_CLK
|
||||
## U1,A14,PS_MIO32_501_USB0_D0
|
||||
## U1,D15,PS_MIO33_501_USB0_D1
|
||||
## U1,A12,PS_MIO34_501_USB0_D2
|
||||
## U1,F12,PS_MIO35_501_USB0_D3
|
||||
## U1,C16,PS_MIO28_501_USB0_D4
|
||||
## U1,A10,PS_MIO37_501_USB0_D5
|
||||
## U1,E13,PS_MIO38_501_USB0_D6
|
||||
## U1,C18,PS_MIO39_501_USB0_D7
|
||||
|
||||
## ddr (fixed-io)
|
||||
## --------------
|
||||
## U1,C2,DDR3_DQS0_P
|
||||
## U1,B2,DDR3_DQS0_N
|
||||
## U1,G2,DDR3_DQS1_P
|
||||
## U1,F2,DDR3_DQS1_N
|
||||
## U1,R2,DDR3_DQS2_P
|
||||
## U1,T2,DDR3_DQS2_N
|
||||
## U1,W5,DDR3_DQS3_P
|
||||
## U1,W4,DDR3_DQS3_N
|
||||
## U1,C3,DDR3_DQ0
|
||||
## U1,B3,DDR3_DQ1
|
||||
## U1,A2,DDR3_DQ2
|
||||
## U1,A4,DDR3_DQ3
|
||||
## U1,D3,DDR3_DQ4
|
||||
## U1,D1,DDR3_DQ5
|
||||
## U1,C1,DDR3_DQ6
|
||||
## U1,E1,DDR3_DQ7
|
||||
## U1,E2,DDR3_DQ8
|
||||
## U1,E3,DDR3_DQ9
|
||||
## U1,G3,DDR3_DQ10
|
||||
## U1,H3,DDR3_DQ11
|
||||
## U1,J3,DDR3_DQ12
|
||||
## U1,H2,DDR3_DQ13
|
||||
## U1,H1,DDR3_DQ14
|
||||
## U1,J1,DDR3_DQ15
|
||||
## U1,P1,DDR3_DQ16
|
||||
## U1,P3,DDR3_DQ17
|
||||
## U1,R3,DDR3_DQ18
|
||||
## U1,R1,DDR3_DQ19
|
||||
## U1,T4,DDR3_DQ20
|
||||
## U1,U4,DDR3_DQ21
|
||||
## U1,U2,DDR3_DQ22
|
||||
## U1,U3,DDR3_DQ23
|
||||
## U1,V1,DDR3_DQ24
|
||||
## U1,Y3,DDR3_DQ25
|
||||
## U1,W1,DDR3_DQ26
|
||||
## U1,Y4,DDR3_DQ27
|
||||
## U1,Y2,DDR3_DQ28
|
||||
## U1,W3,DDR3_DQ29
|
||||
## U1,V2,DDR3_DQ30
|
||||
## U1,V3,DDR3_DQ31
|
||||
## U1,A1,DDR3_DM0
|
||||
## U1,F1,DDR3_DM1
|
||||
## U1,T1,DDR3_DM2
|
||||
## U1,Y1,DDR3_DM3
|
||||
## U1,N2,DDR3_A0
|
||||
## U1,K2,DDR3_A1
|
||||
## U1,M3,DDR3_A2
|
||||
## U1,K3,DDR3_A3
|
||||
## U1,M4,DDR3_A4
|
||||
## U1,L1,DDR3_A5
|
||||
## U1,L4,DDR3_A6
|
||||
## U1,K4,DDR3_A7
|
||||
## U1,K1,DDR3_A8
|
||||
## U1,J4,DDR3_A9
|
||||
## U1,F5,DDR3_A10
|
||||
## U1,G4,DDR3_A11
|
||||
## U1,E4,DDR3_A12
|
||||
## U1,D4,DDR3_A13
|
||||
## U1,F4,DDR3_A14
|
||||
## U1,L5,DDR3_BA0
|
||||
## U1,R4,DDR3_BA1
|
||||
## U1,J5,DDR3_BA2
|
||||
## U1,L2,DDR3_CK_P
|
||||
## U1,M2,DDR3_CK_N
|
||||
## U1,N3,DDR3_CKE
|
||||
## U1,B4,DDR3_RST#
|
||||
## U1,N1,DDR3_CS#
|
||||
## U1,M5,DDR3_WE#
|
||||
## U1,P4,DDR3_RAS#
|
||||
## U1,P5,DDR3_CAS#
|
||||
## U1,N5,DDR3_ODT
|
||||
|
||||
## resets, clock and power controls
|
||||
## --------------------------------
|
||||
## U1,E7,UNNAMED_3_ICXC7Z20_I217_PSCLK50,33.33MEGHZ
|
||||
## U1,B10,PS-SRST#
|
||||
## U1,C7,PWR_GD_1.35V
|
||||
## JX2,10,PG_1P8V
|
||||
## JX2,11,PG_MODULE
|
||||
## JX1,5,PWR_ENABLE
|
||||
## JX1,6,CARRIER_RESET
|
||||
|
||||
## JTAG
|
||||
## ----
|
||||
## U1,J6,JTAG_TMS,JX1,2,JTAG_TMS
|
||||
## U1,F9,JTAG_TCK,JX1,1,JTAG_TCK
|
||||
## U1,F6,JTAG_TDO,JX1,3,JTAG_TDO
|
||||
## U1,G6,JTAG_TDI,JX1,4,JTAG_TDI
|
||||
## U1,R11,FPGA_DONE,JX1,8,CFG_DONE
|
||||
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
|
||||
# constraints (pzsdr1.b)
|
||||
# ad9361 (SWAP == 0x0)
|
||||
|
||||
set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS25} [get_ports rx_clk_in] ; ## IO_L12P_T1_MRCC_35 U1,K17,IO_L12_MRCC_35_DATA_CLK_P
|
||||
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports rx_frame_in] ; ## IO_L7P_T1_AD2P_35 U1,M19,IO_L07_35_RX_FRAME_P
|
||||
set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS25} [get_ports rx_data_in[0]] ; ## IO_L13N_T2_MRCC_35 U1,H17,IO_L13_35_TX_D0_N
|
||||
set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS25} [get_ports rx_data_in[1]] ; ## IO_L13P_T2_MRCC_35 U1,H16,IO_L13_35_TX_D0_P
|
||||
set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVCMOS25} [get_ports rx_data_in[2]] ; ## IO_L14N_T2_AD4N_SRCC_35 U1,H18,IO_L14_35_TX_D1_N
|
||||
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports rx_data_in[3]] ; ## IO_L14P_T2_AD4P_SRCC_35 U1,J18,IO_L14_35_TX_D1_P
|
||||
set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVCMOS25} [get_ports rx_data_in[4]] ; ## IO_L15N_T2_DQS_AD12N_35 U1,F20,IO_L15_35_TX_D2_N
|
||||
set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS25} [get_ports rx_data_in[5]] ; ## IO_L15P_T2_DQS_AD12P_35 U1,F19,IO_L15_35_TX_D2_P
|
||||
set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS25} [get_ports rx_data_in[6]] ; ## IO_L16N_T2_35 U1,G18,IO_L16_35_TX_D3_N
|
||||
set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS25} [get_ports rx_data_in[7]] ; ## IO_L16P_T2_35 U1,G17,IO_L16_35_TX_D3_P
|
||||
set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVCMOS25} [get_ports rx_data_in[8]] ; ## IO_L17N_T2_AD5N_35 U1,H20,IO_L17_35_TX_D4_N
|
||||
set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports rx_data_in[9]] ; ## IO_L17P_T2_AD5P_35 U1,J20,IO_L17_35_TX_D4_P
|
||||
set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS25} [get_ports rx_data_in[10]] ; ## IO_L18N_T2_AD13N_35 U1,G20,IO_L18_35_TX_D5_N
|
||||
set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS25} [get_ports rx_data_in[11]] ; ## IO_L18P_T2_AD13P_35 U1,G19,IO_L18_35_TX_D5_P
|
||||
|
||||
set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports tx_clk_out] ; ## IO_L8P_T1_AD10P_35 U1,M17,IO_L08_35_FB_CLK_P
|
||||
set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS25} [get_ports tx_frame_out] ; ## IO_L9P_T1_DQS_AD3P_35 U1,L19,IO_L09_35_TX_FRAME_P
|
||||
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports tx_data_out[0]] ; ## IO_L1N_T0_AD0N_35 U1,B20,IO_L01_35_RX_D0_N
|
||||
set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS25} [get_ports tx_data_out[1]] ; ## IO_L1P_T0_AD0P_35 U1,C20,IO_L01_35_RX_D0_P
|
||||
set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS25} [get_ports tx_data_out[2]] ; ## IO_L2N_T0_AD8N_35 U1,A20,IO_L02_35_RX_D1_N
|
||||
set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports tx_data_out[3]] ; ## IO_L2P_T0_AD8P_35 U1,B19,IO_L02_35_RX_D1_P
|
||||
set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS25} [get_ports tx_data_out[4]] ; ## IO_L3N_T0_DQS_AD1N_35 U1,D18,IO_L03_35_RX_D2_N
|
||||
set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS25} [get_ports tx_data_out[5]] ; ## IO_L3P_T0_DQS_AD1P_35 U1,E17,IO_L03_35_RX_D2_P
|
||||
set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25} [get_ports tx_data_out[6]] ; ## IO_L4N_T0_35 U1,D20,IO_L04_35_RX_D3_N
|
||||
set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS25} [get_ports tx_data_out[7]] ; ## IO_L4P_T0_35 U1,D19,IO_L04_35_RX_D3_P
|
||||
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports tx_data_out[8]] ; ## IO_L5N_T0_AD9N_35 U1,E19,IO_L05_35_RX_D4_N
|
||||
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports tx_data_out[9]] ; ## IO_L5P_T0_AD9P_35 U1,E18,IO_L05_35_RX_D4_P
|
||||
set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS25} [get_ports tx_data_out[10]] ; ## IO_L6N_T0_VREF_35 U1,F17,IO_L06_35_RX_D5_N
|
||||
set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS25} [get_ports tx_data_out[11]] ; ## IO_L6P_T0_35 U1,F16,IO_L06_35_RX_D5_P
|
||||
|
||||
set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS25} [get_ports tx_gnd[0]] ; ## IO_L8N_T1_AD10N_35 U1,M18,IO_L08_35_FB_CLK_N
|
||||
set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS25} [get_ports tx_gnd[1]] ; ## IO_L9N_T1_DQS_AD3N_35 U1,L20,IO_L09_35_TX_FRAME_N
|
||||
|
||||
# clocks
|
||||
|
||||
create_clock -name rx_clk -period 8 [get_ports rx_clk_in]
|
||||
create_clock -name ad9361_clk -period 8 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
|
||||
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
|
||||
# constraints (pzsdr1.b)
|
||||
# ad9361
|
||||
|
||||
set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## IO_L12P_T1_MRCC_35 U1,K17,IO_L12_MRCC_35_DATA_CLK_P
|
||||
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## IO_L12N_T1_MRCC_35 U1,K18,IO_L12_MRCC_35_DATA_CLK_N
|
||||
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## IO_L7P_T1_AD2P_35 U1,M19,IO_L07_35_RX_FRAME_P
|
||||
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## IO_L7N_T1_AD2N_35 U1,M20,IO_L07_35_RX_FRAME_N
|
||||
set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## IO_L1P_T0_AD0P_35 U1,C20,IO_L01_35_RX_D0_P
|
||||
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## IO_L1N_T0_AD0N_35 U1,B20,IO_L01_35_RX_D0_N
|
||||
set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## IO_L2P_T0_AD8P_35 U1,B19,IO_L02_35_RX_D1_P
|
||||
set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## IO_L2N_T0_AD8N_35 U1,A20,IO_L02_35_RX_D1_N
|
||||
set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## IO_L3P_T0_DQS_AD1P_35 U1,E17,IO_L03_35_RX_D2_P
|
||||
set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## IO_L3N_T0_DQS_AD1N_35 U1,D18,IO_L03_35_RX_D2_N
|
||||
set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## IO_L4P_T0_35 U1,D19,IO_L04_35_RX_D3_P
|
||||
set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## IO_L4N_T0_35 U1,D20,IO_L04_35_RX_D3_N
|
||||
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## IO_L5P_T0_AD9P_35 U1,E18,IO_L05_35_RX_D4_P
|
||||
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## IO_L5N_T0_AD9N_35 U1,E19,IO_L05_35_RX_D4_N
|
||||
set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## IO_L6P_T0_35 U1,F16,IO_L06_35_RX_D5_P
|
||||
set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## IO_L6N_T0_VREF_35 U1,F17,IO_L06_35_RX_D5_N
|
||||
set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVDS_25} [get_ports tx_clk_out_p] ; ## IO_L8P_T1_AD10P_35 U1,M17,IO_L08_35_FB_CLK_P
|
||||
set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVDS_25} [get_ports tx_clk_out_n] ; ## IO_L8N_T1_AD10N_35 U1,M18,IO_L08_35_FB_CLK_N
|
||||
set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVDS_25} [get_ports tx_frame_out_p] ; ## IO_L9P_T1_DQS_AD3P_35 U1,L19,IO_L09_35_TX_FRAME_P
|
||||
set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVDS_25} [get_ports tx_frame_out_n] ; ## IO_L9N_T1_DQS_AD3N_35 U1,L20,IO_L09_35_TX_FRAME_N
|
||||
set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[0]] ; ## IO_L13P_T2_MRCC_35 U1,H16,IO_L13_35_TX_D0_P
|
||||
set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[0]] ; ## IO_L13N_T2_MRCC_35 U1,H17,IO_L13_35_TX_D0_N
|
||||
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[1]] ; ## IO_L14P_T2_AD4P_SRCC_35 U1,J18,IO_L14_35_TX_D1_P
|
||||
set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[1]] ; ## IO_L14N_T2_AD4N_SRCC_35 U1,H18,IO_L14_35_TX_D1_N
|
||||
set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[2]] ; ## IO_L15P_T2_DQS_AD12P_35 U1,F19,IO_L15_35_TX_D2_P
|
||||
set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[2]] ; ## IO_L15N_T2_DQS_AD12N_35 U1,F20,IO_L15_35_TX_D2_N
|
||||
set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[3]] ; ## IO_L16P_T2_35 U1,G17,IO_L16_35_TX_D3_P
|
||||
set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[3]] ; ## IO_L16N_T2_35 U1,G18,IO_L16_35_TX_D3_N
|
||||
set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[4]] ; ## IO_L17P_T2_AD5P_35 U1,J20,IO_L17_35_TX_D4_P
|
||||
set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[4]] ; ## IO_L17N_T2_AD5N_35 U1,H20,IO_L17_35_TX_D4_N
|
||||
set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[5]] ; ## IO_L18P_T2_AD13P_35 U1,G19,IO_L18_35_TX_D5_P
|
||||
set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[5]] ; ## IO_L18N_T2_AD13N_35 U1,G20,IO_L18_35_TX_D5_N
|
||||
|
||||
# clocks
|
||||
|
||||
create_clock -name rx_clk -period 4 [get_ports rx_clk_in_p]
|
||||
create_clock -name ad9361_clk -period 4 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
|
||||
|
||||
Loading…
Reference in New Issue