diff --git a/projects/daq2/a10gx/system_bd.qsys b/projects/daq2/a10gx/system_bd.qsys
index 31167c710..eb6934cc4 100755
--- a/projects/daq2/a10gx/system_bd.qsys
+++ b/projects/daq2/a10gx/system_bd.qsys
@@ -103,7 +103,7 @@
{
datum _sortIndex
{
- value = "22";
+ value = "20";
type = "int";
}
}
@@ -405,68 +405,36 @@
type = "String";
}
}
- element sys_xcvr
+ element system_bd
{
- datum _sortIndex
+ datum _originalDeviceFamily
{
- value = "23";
- type = "int";
- }
- }
- element sys_xcvr.jesd204_rx_avs
- {
- datum baseAddress
- {
- value = "0";
+ value = "Arria 10";
type = "String";
}
}
- element sys_xcvr_rstcntrl
+ element system_bd
{
- datum _sortIndex
+ datum _originalDeviceFamily
{
- value = "24";
- type = "int";
+ value = "Arria 10";
+ type = "String";
}
}
- element sys_xcvr_rx_clk
+ element system_bd
{
- datum _sortIndex
+ datum _originalDeviceFamily
{
- value = "25";
- type = "int";
+ value = "Arria 10";
+ type = "String";
}
}
- element sys_xcvr_rx_ref_clk
+ element system_bd
{
- datum _sortIndex
+ datum _originalDeviceFamily
{
- value = "26";
- type = "int";
- }
- }
- element sys_xcvr_tx_clk
- {
- datum _sortIndex
- {
- value = "27";
- type = "int";
- }
- }
- element sys_xcvr_tx_pll
- {
- datum _sortIndex
- {
- value = "28";
- type = "int";
- }
- }
- element sys_xcvr_tx_ref_clk
- {
- datum _sortIndex
- {
- value = "29";
- type = "int";
+ value = "Arria 10";
+ type = "String";
}
}
element system_bd
@@ -629,22 +597,6 @@
type = "String";
}
}
- element util_jesd_align
- {
- datum _sortIndex
- {
- value = "21";
- type = "int";
- }
- }
- element util_jesd_xmit
- {
- datum _sortIndex
- {
- value = "20";
- type = "int";
- }
- }
element util_upack_0
{
datum _sortIndex
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- GX clock output buffer
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- altera_xcvr_atx_pll_a10
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+ start="axi_jesd_xcvr.if_tx_clk"
+ end="util_upack_0.if_dac_clk" />
+ start="axi_jesd_xcvr.if_tx_clk"
+ end="axi_ad9144_dma.if_fifo_rd_clk" />
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+ start="axi_ad9680_core.if_rx_data"
+ end="axi_jesd_xcvr.if_rx_data">
@@ -3406,199 +2558,14 @@
+ start="axi_jesd_xcvr.if_tx_data"
+ end="axi_ad9144_core.if_tx_data">
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diff --git a/projects/daq2/a10gx/system_project.tcl b/projects/daq2/a10gx/system_project.tcl
index 56adf150e..367f44b8c 100755
--- a/projects/daq2/a10gx/system_project.tcl
+++ b/projects/daq2/a10gx/system_project.tcl
@@ -8,6 +8,14 @@ source $ad_hdl_dir/projects/common/a10gx/a10gx_system_assign.tcl
set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/ad_iobuf.v
set_global_assignment -name VERILOG_FILE ../common/daq2_spi.v
+set_global_assignment -name VERILOG_FILE ../common/sys_xcvr.v
+set_global_assignment -name QSYS_FILE ../common/sys_xcvr_tx_lane_pll.qsys
+set_global_assignment -name QSYS_FILE ../common/sys_xcvr_core.qsys
+set_global_assignment -name QSYS_FILE ../common/sys_xcvr_rstcntrl.qsys
+set_global_assignment -name QSYS_FILE ../common/sys_xcvr_rx_pll.qsys
+set_global_assignment -name QSYS_FILE ../common/sys_xcvr_tx_pll.qsys
+set_global_assignment -name QSYS_FILE ../common/sys_xcvr_rx_ip.qsys
+set_global_assignment -name QSYS_FILE ../common/sys_xcvr_tx_ip.qsys
# lane interface
diff --git a/projects/daq2/a10gx/system_top.v b/projects/daq2/a10gx/system_top.v
index 9d75b7690..428d5f6a7 100644
--- a/projects/daq2/a10gx/system_top.v
+++ b/projects/daq2/a10gx/system_top.v
@@ -239,10 +239,13 @@ module system_top (
.dio_p (gpio_bd));
system_bd i_system_bd (
- .rx_data_rx_serial_data (rx_data),
+ .rx_data_rx_d (rx_data),
.rx_ref_clk_clk (rx_ref_clk),
.rx_sync_rx_sync (rx_sync),
.rx_sysref_rx_ext_sysref (rx_sysref),
+ .stp_clk_clk (),
+ .stp_data_stp_data (),
+ .stp_trigger_stp_trigger (),
.sys_clk_clk (sys_clk),
.sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
.sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
@@ -277,7 +280,7 @@ module system_top (
.sys_spi_MOSI (spi_mosi_s),
.sys_spi_SCLK (spi_clk),
.sys_spi_SS_n (spi_csn_s),
- .tx_data_tx_serial_data (tx_data),
+ .tx_data_tx_d (tx_data),
.tx_ref_clk_clk (tx_ref_clk),
.tx_sync_tx_sync (tx_sync),
.tx_sysref_tx_ext_sysref (tx_sysref));