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fmcjesdadc1/a5gt- qr to ddio max delay

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Rejeesh Kutty 2017-01-04 14:10:44 -05:00
parent e4e5b30ade
commit 8b74e911b8
1 changed files with 3 additions and 0 deletions
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3
projects/fmcjesdadc1/a5gt/system_constr.sdc
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@ -25,3 +25,6 @@ set_false_path -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPU
set_false_path -from [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] \
-through [get_nets *altera_jesd204_rx_csr_inst*] -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}]
set_max_delay -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll8~PLL_OUTPUT_COUNTER|divclk}] \
-to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll4~PLL_OUTPUT_COUNTER|divclk}] 2