From 8b74e911b8c69ecfd63d63219d8867bac53e96db Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Wed, 4 Jan 2017 14:10:44 -0500 Subject: [PATCH] fmcjesdadc1/a5gt- qr to ddio max delay --- projects/fmcjesdadc1/a5gt/system_constr.sdc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/projects/fmcjesdadc1/a5gt/system_constr.sdc b/projects/fmcjesdadc1/a5gt/system_constr.sdc index f6da22797..9d7fdd72a 100644 --- a/projects/fmcjesdadc1/a5gt/system_constr.sdc +++ b/projects/fmcjesdadc1/a5gt/system_constr.sdc @@ -25,3 +25,6 @@ set_false_path -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPU set_false_path -from [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] \ -through [get_nets *altera_jesd204_rx_csr_inst*] -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}] +set_max_delay -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll8~PLL_OUTPUT_COUNTER|divclk}] \ + -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll4~PLL_OUTPUT_COUNTER|divclk}] 2 +