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axi_damc: Add xfer_req to the FIFO source interface 

The xfer_req signal will be high if DMA core the is expecting data.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2014-07-02 16:03:18 +02:00
parent 60dd14bcdb
commit 8a2b29cdbe
4 changed files with 12 additions and 1 deletions
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2
library/axi_dmac/axi_dmac.v
View File

@ -125,6 +125,7 @@ module axi_dmac (
input [C_DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din,
output fifo_wr_overflow,
input fifo_wr_sync,
output fifo_wr_xfer_req,
// Input FIFO interface
input fifo_rd_clk,
@ -546,6 +547,7 @@ dmac_request_arb #(
.fifo_wr_din(fifo_wr_din),
.fifo_wr_overflow(fifo_wr_overflow),
.fifo_wr_sync(fifo_wr_sync),
.fifo_wr_xfer_req(fifo_wr_xfer_req),
.fifo_rd_clk(fifo_rd_clk),

4
library/axi_dmac/data_mover.v
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@ -48,6 +48,8 @@ module dmac_data_mover (
input enable,
output reg enabled,
output xfer_req,
output s_axi_ready,
input s_axi_valid,
input [C_DATA_WIDTH-1:0] s_axi_data,
@ -83,6 +85,8 @@ reg last_non_eot = 1'b0;
wire last_load;
wire last;
assign xfer_req = active;
assign response_id = id;
assign last = eot ? last_eot : last_non_eot;

4
library/axi_dmac/request_arb.v
View File

@ -115,6 +115,7 @@ module dmac_request_arb (
input [C_DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din,
output fifo_wr_overflow,
input fifo_wr_sync,
output fifo_wr_xfer_req,
// Input FIFO interface
input fifo_rd_clk,
@ -742,7 +743,8 @@ dmac_src_fifo_inf #(
.en(fifo_wr_en),
.din(fifo_wr_din),
.overflow(fifo_wr_overflow),
.sync(fifo_wr_sync)
.sync(fifo_wr_sync),
.xfer_req(fifo_wr_xfer_req)
);
end else begin

3
library/axi_dmac/src_fifo_inf.v
View File

@ -53,6 +53,7 @@ module dmac_src_fifo_inf (
input [C_DATA_WIDTH-1:0] din,
output reg overflow,
input sync,
output xfer_req,
input fifo_ready,
output fifo_valid,
@ -134,6 +135,8 @@ dmac_data_mover # (
.enabled(enabled),
.sync_id(sync_id),
.xfer_req(xfer_req),
.request_id(request_id),
.response_id(response_id),
.eot(eot),