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arradio: Fix the last incorrect merge

main
Istvan Csomortani 2017-10-03 09:14:42 +01:00
parent 08a31a7d9f
commit 899b8436ad
1 changed files with 12 additions and 20 deletions
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32
projects/arradio/common/arradio_qsys.tcl
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@ -20,12 +20,6 @@ add_connection sys_clk.clk axi_ad9361.if_delay_clk
add_connection sys_clk.clk axi_ad9361.s_axi_clock
add_connection sys_clk.clk_reset axi_ad9361.s_axi_reset
# clk division
add_instance util_clkdiv_ad9361 util_clkdiv 1.0
add_connection axi_ad9361.if_l_clk util_clkdiv_ad9361.if_clk
add_connection axi_ad9361.if_rst util_clkdiv_ad9361.if_reset
# adc-wfifo & dac-rfifo
add_instance util_adc_wfifo util_wfifo
@ -35,8 +29,8 @@ set_instance_parameter_value util_adc_wfifo {DOUT_DATA_WIDTH} {16}
set_instance_parameter_value util_adc_wfifo {DIN_ADDRESS_WIDTH} {5}
add_connection axi_ad9361.if_l_clk util_adc_wfifo.if_din_clk
add_connection axi_ad9361.if_rst util_adc_wfifo.if_din_rst
add_connection util_clkdiv_ad9361.if_clk_out util_adc_wfifo.if_dout_clk
add_connection util_clkdiv_ad9361.if_reset_out util_adc_wfifo.if_dout_rstn
add_connection sys_dma_clk.clk util_adc_wfifo.if_dout_clk
add_connection sys_dma_clk.clk_reset util_adc_wfifo.if_dout_rstn
add_connection axi_ad9361.adc_ch_0 util_adc_wfifo.din_0
add_connection axi_ad9361.adc_ch_1 util_adc_wfifo.din_1
add_connection axi_ad9361.adc_ch_2 util_adc_wfifo.din_2
@ -52,8 +46,8 @@ set_instance_parameter_value util_dac_rfifo {DOUT_DATA_WIDTH} {16}
set_instance_parameter_value util_dac_rfifo {DIN_ADDRESS_WIDTH} {5}
add_connection axi_ad9361.if_l_clk util_dac_rfifo.if_dout_clk
add_connection axi_ad9361.if_rst util_dac_rfifo.if_dout_rst
add_connection util_clkdiv_ad9361.if_clk_out util_dac_rfifo.if_din_clk
add_connection util_clkdiv_ad9361.if_reset_out util_dac_rfifo.if_din_rstn
add_connection sys_dma_clk.clk util_dac_rfifo.if_din_clk
add_connection sys_dma_clk.clk_reset util_dac_rfifo.if_din_rstn
add_connection util_dac_rfifo.dout_0 axi_ad9361.dac_ch_0
add_connection util_dac_rfifo.dout_1 axi_ad9361.dac_ch_1
add_connection util_dac_rfifo.dout_2 axi_ad9361.dac_ch_2
@ -65,8 +59,8 @@ add_connection util_dac_rfifo.if_dout_unf axi_ad9361.if_dac_dunf
add_instance util_adc_pack util_cpack
set_instance_parameter_value util_adc_pack {NUM_OF_CHANNELS} {4}
set_instance_parameter_value util_adc_pack {CHANNEL_DATA_WIDTH} {16}
add_connection util_clkdiv_ad9361.if_clk_out util_adc_pack.if_adc_clk
add_connection util_clkdiv_ad9361.if_reset_out util_adc_pack.if_adc_rst
add_connection sys_dma_clk.clk util_adc_pack.if_adc_clk
add_connection sys_dma_clk.clk_reset util_adc_pack.if_adc_rst
add_connection util_adc_wfifo.dout_0 util_adc_pack.adc_ch_0
add_connection util_adc_wfifo.dout_1 util_adc_pack.adc_ch_1
add_connection util_adc_wfifo.dout_2 util_adc_pack.adc_ch_2
@ -77,7 +71,7 @@ add_connection util_adc_wfifo.dout_3 util_adc_pack.adc_ch_3
add_instance util_dac_upack util_upack
set_instance_parameter_value util_dac_upack {NUM_OF_CHANNELS} {4}
set_instance_parameter_value util_dac_upack {CHANNEL_DATA_WIDTH} {16}
add_connection util_clkdiv_ad9361.if_clk_out util_dac_upack.if_dac_clk
add_connection sys_dma_clk.clk util_dac_upack.if_dac_clk
add_connection util_dac_upack.dac_ch_0 util_dac_rfifo.din_0
add_connection util_dac_upack.dac_ch_1 util_dac_rfifo.din_1
add_connection util_dac_upack.dac_ch_2 util_dac_rfifo.din_2
@ -88,7 +82,7 @@ add_connection util_dac_upack.dac_ch_3 util_dac_rfifo.din_3
add_instance axi_adc_dma axi_dmac
set_instance_parameter_value axi_adc_dma {ID} {0}
set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_SRC} {64}
set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_DEST} {128}
set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_DEST} {64}
set_instance_parameter_value axi_adc_dma {DMA_LENGTH_WIDTH} {24}
set_instance_parameter_value axi_adc_dma {DMA_2D_TRANSFER} {0}
set_instance_parameter_value axi_adc_dma {AXI_SLICE_DEST} {0}
@ -102,7 +96,7 @@ add_connection sys_clk.clk axi_adc_dma.s_axi_clock
add_connection sys_clk.clk_reset axi_adc_dma.s_axi_reset
add_connection sys_dma_clk.clk axi_adc_dma.m_dest_axi_clock
add_connection sys_dma_clk.clk_reset axi_adc_dma.m_dest_axi_reset
add_connection util_clkdiv_ad9361.if_clk_out axi_adc_dma.if_fifo_wr_clk
add_connection sys_dma_clk.clk axi_adc_dma.if_fifo_wr_clk
add_connection util_adc_pack.if_adc_valid axi_adc_dma.if_fifo_wr_en
add_connection util_adc_pack.if_adc_sync axi_adc_dma.if_fifo_wr_sync
add_connection util_adc_pack.if_adc_data axi_adc_dma.if_fifo_wr_din
@ -127,7 +121,7 @@ add_connection sys_clk.clk axi_dac_dma.s_axi_clock
add_connection sys_clk.clk_reset axi_dac_dma.s_axi_reset
add_connection sys_dma_clk.clk axi_dac_dma.m_src_axi_clock
add_connection sys_dma_clk.clk_reset axi_dac_dma.m_src_axi_reset
add_connection util_clkdiv_ad9361.if_clk_out axi_dac_dma.if_fifo_rd_clk
add_connection sys_dma_clk.clk axi_dac_dma.if_fifo_rd_clk
add_connection util_dac_upack.if_dac_valid axi_dac_dma.if_fifo_rd_en
add_connection axi_dac_dma.if_fifo_rd_dout util_dac_upack.if_dac_data
add_connection axi_dac_dma.if_fifo_rd_underflow util_dac_rfifo.if_din_unf
@ -145,8 +139,6 @@ ad_cpu_interconnect 0x00104000 axi_dac_dma.s_axi
# mem interconnects
set_instance_parameter_value sys_hps {F2SDRAM_Width} {64 128 64}
ad_dma_interconnect axi_adc_dma.m_dest_axi 1
ad_dma_interconnect axi_dac_dma.m_src_axi 2
ad_dma_interconnect axi_adc_dma.m_dest_axi 0
ad_dma_interconnect axi_dac_dma.m_src_axi 1