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ad_dds_2: Remove unused disable logic feature

main
AndreiGrozav 2018-06-27 15:06:38 +01:00 committed by AndreiGrozav
parent 8a306ce96b
commit 892febe68a
1 changed files with 60 additions and 67 deletions
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21
library/common/ad_dds_2.v
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@ -87,13 +87,7 @@ module ad_dds_2 #(
wire [DDS_P_DW-1:0] dds_phase_0_s;
wire [DDS_P_DW-1:0] dds_phase_1_s;
// disable DDS
generate
if (DISABLE == 1) begin
// assign 0 for the exact buss width to avoid warnings
assign dds_data = {DDS_DW{1'b0}};
end else begin
// dds channel output
assign dds_data = dds_data_out;
@ -125,20 +119,20 @@ module ad_dds_2 #(
end
// phase
if (DDS_P_DW >= PHASE_DW) begin
assign dds_phase_0_s = {dds_phase_0,{DDS_P_DW-(PHASE_DW-1){1'b0}}};
assign dds_phase_1_s = {dds_phase_1,{DDS_P_DW-(PHASE_DW-1){1'b0}}};
if (DDS_P_DW > PHASE_DW) begin
assign dds_phase_0_s = {dds_phase_0,{DDS_P_DW-PHASE_DW{1'b0}}};
assign dds_phase_1_s = {dds_phase_1,{DDS_P_DW-PHASE_DW{1'b0}}};
end else begin
assign dds_phase_0_s = {dds_phase_0[(PHASE_DW-1):PHASE_DW-DDS_P_DW],1'b0};
assign dds_phase_1_s = {dds_phase_1[(PHASE_DW-1):PHASE_DW-DDS_P_DW],1'b0};
assign dds_phase_0_s = dds_phase_0[(PHASE_DW-1):PHASE_DW-DDS_P_DW];
assign dds_phase_1_s = dds_phase_1[(PHASE_DW-1):PHASE_DW-DDS_P_DW];
end
// dds-1
ad_dds_1 #(
.DDS_TYPE(DDS_TYPE),
.DDS_D_DW(CORDIC_DW),
.DDS_P_DW(CORDIC_PHASE_DW))
.DDS_D_DW(DDS_D_DW),
.DDS_P_DW(DDS_P_DW))
i_dds_1_0 (
.clk (clk),
.angle (dds_phase_0_s),
@ -156,7 +150,6 @@ module ad_dds_2 #(
.angle (dds_phase_1_s),
.scale (dds_scale_1_d),
.dds_data (dds_data_1_s));
end
endgenerate
endmodule