From 88b5c2d6db7419d3b5405e83e87dd8f090becfeb Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Tue, 17 Mar 2020 08:15:01 +0000 Subject: [PATCH] projects/common/vcu128: Initial VCU128 support --- projects/common/vcu128/vcu128_system_bd.tcl | 303 ++++++++++++++++++ .../common/vcu128/vcu128_system_constr.xdc | 59 ++++ projects/scripts/adi_project_xilinx.tcl | 6 +- 3 files changed, 367 insertions(+), 1 deletion(-) create mode 100644 projects/common/vcu128/vcu128_system_bd.tcl create mode 100644 projects/common/vcu128/vcu128_system_constr.xdc diff --git a/projects/common/vcu128/vcu128_system_bd.tcl b/projects/common/vcu128/vcu128_system_bd.tcl new file mode 100644 index 000000000..fce01e8e0 --- /dev/null +++ b/projects/common/vcu128/vcu128_system_bd.tcl @@ -0,0 +1,303 @@ + +# create board design +# interface ports + +create_bd_port -dir I -type rst sys_rst + +create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk + +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4 + +create_bd_port -dir I phy_sd +create_bd_port -dir O -type rst phy_rst_n +create_bd_port -dir I phy_dummy_port_in + +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:sgmii_rtl:1.0 sgmii +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 mdio +create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sgmii_phyclk +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main + +create_bd_port -dir I uart_sin +create_bd_port -dir O uart_sout + +create_bd_port -dir O -from 7 -to 0 spi_csn_o +create_bd_port -dir I -from 7 -to 0 spi_csn_i +create_bd_port -dir I spi_clk_i +create_bd_port -dir O spi_clk_o +create_bd_port -dir I spi_sdo_i +create_bd_port -dir O spi_sdo_o +create_bd_port -dir I spi_sdi_i + +create_bd_port -dir I -from 31 -to 0 gpio0_i +create_bd_port -dir O -from 31 -to 0 gpio0_o +create_bd_port -dir O -from 31 -to 0 gpio0_t +create_bd_port -dir I -from 31 -to 0 gpio1_i +create_bd_port -dir O -from 31 -to 0 gpio1_o +create_bd_port -dir O -from 31 -to 0 gpio1_t + +# io settings + +set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] [get_bd_ports sys_rst] +set_property -dict [list CONFIG.FREQ_HZ {100000000}] [get_bd_intf_ports sys_clk] +set_property -dict [list CONFIG.FREQ_HZ {625000000}] [get_bd_intf_ports sgmii_phyclk] + +# instance: microblaze - processor + +ad_ip_instance microblaze sys_mb +ad_ip_parameter sys_mb CONFIG.G_TEMPLATE_LIST 4 +ad_ip_parameter sys_mb CONFIG.C_DCACHE_FORCE_TAG_LUTRAM 1 + +# instance: microblaze - local memory & bus + +ad_ip_instance lmb_v10 sys_dlmb +ad_ip_instance lmb_v10 sys_ilmb + +ad_ip_instance lmb_bram_if_cntlr sys_dlmb_cntlr +ad_ip_parameter sys_dlmb_cntlr CONFIG.C_ECC {0} + +ad_ip_instance lmb_bram_if_cntlr sys_ilmb_cntlr +ad_ip_parameter sys_ilmb_cntlr CONFIG.C_ECC {0} + +ad_ip_instance blk_mem_gen sys_lmb_bram +ad_ip_parameter sys_lmb_bram CONFIG.Memory_Type True_Dual_Port_RAM +ad_ip_parameter sys_lmb_bram CONFIG.use_bram_block BRAM_Controller + +# instance: microblaze- mdm + +ad_ip_instance mdm sys_mb_debug +ad_ip_parameter sys_mb_debug CONFIG.C_USE_UART 1 + +# instance: system reset/clocks +ad_ip_instance proc_sys_reset sys_rstgen +ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1 +ad_ip_instance proc_sys_reset sys_250m_rstgen +ad_ip_parameter sys_250m_rstgen CONFIG.C_EXT_RST_WIDTH 1 +ad_ip_instance proc_sys_reset sys_500m_rstgen +ad_ip_parameter sys_500m_rstgen CONFIG.C_EXT_RST_WIDTH 1 + +# instance: ddr4 +# +ad_ip_instance ip:ddr4 axi_ddr_cntrl +ad_ip_parameter axi_ddr_cntrl CONFIG.C0_CLOCK_BOARD_INTERFACE {default_100mhz_clk} +ad_ip_parameter axi_ddr_cntrl CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram} +ad_ip_parameter axi_ddr_cntrl ONFIG.RESET_BOARD_INTERFACE {reset} +ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_Clamshell {true} +ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_InputClockPeriod {10000} +ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_CLKOUT0_DIVIDE {3} +ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-075E} +ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_DataWidth {72} +ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} +ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_Ecc {true} +ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_AxiDataWidth {512} +ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_AxiAddressWidth {32} +ad_ip_parameter axi_ddr_cntrl CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} +ad_ip_parameter axi_ddr_cntrl CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ 250 +ad_ip_parameter axi_ddr_cntrl CONFIG.ADDN_UI_CLKOUT3_FREQ_HZ 500 +ad_ip_parameter axi_ddr_cntrl CONFIG.C0.BANK_GROUP_WIDTH {1} +ad_ip_parameter axi_ddr_cntrl CONFIG.C0.CS_WIDTH {2} + +ad_ip_instance proc_sys_reset axi_ddr_cntrl_rstgen + +# instance: default peripherals + +ad_ip_instance axi_ethernet axi_ethernet_0 +ad_ip_parameter axi_ethernet_0 CONFIG.DIFFCLK_BOARD_INTERFACE sgmii_phyclk +ad_ip_parameter axi_ethernet_0 CONFIG.ETHERNET_BOARD_INTERFACE sgmii_lvds +ad_ip_parameter axi_ethernet_0 CONFIG.MDIO_BOARD_INTERFACE mdio_mdc +ad_ip_parameter axi_ethernet_0 CONFIG.PHYRST_BOARD_INTERFACE_DUMMY_PORT dummy_port_in +ad_ip_parameter axi_ethernet_0 CONFIG.TXCSUM Full +ad_ip_parameter axi_ethernet_0 CONFIG.RXCSUM Full +ad_ip_parameter axi_ethernet_0 CONFIG.TXMEM 8k +ad_ip_parameter axi_ethernet_0 CONFIG.RXMEM 8k + +ad_ip_instance axi_dma axi_ethernet_dma +ad_ip_parameter axi_ethernet_dma CONFIG.c_include_mm2s_dre 1 +ad_ip_parameter axi_ethernet_dma CONFIG.c_sg_use_stsapp_length 1 +ad_ip_parameter axi_ethernet_dma CONFIG.c_include_s2mm_dre 1 + +ad_ip_instance axi_iic axi_iic_main + +ad_ip_instance axi_uartlite axi_uart +ad_ip_parameter axi_uart CONFIG.C_BAUDRATE 115200 + +ad_ip_instance axi_timer axi_timer + +ad_ip_instance axi_quad_spi axi_spi +ad_ip_parameter axi_spi CONFIG.C_USE_STARTUP 0 +ad_ip_parameter axi_spi CONFIG.C_NUM_SS_BITS 8 +ad_ip_parameter axi_spi CONFIG.C_SCK_RATIO 8 + +ad_ip_instance axi_gpio axi_gpio +ad_ip_parameter axi_gpio CONFIG.C_IS_DUAL 1 +ad_ip_parameter axi_gpio CONFIG.C_GPIO_WIDTH 32 +ad_ip_parameter axi_gpio CONFIG.C_GPIO2_WIDTH 32 +ad_ip_parameter axi_gpio CONFIG.C_INTERRUPT_PRESENT 1 + +# instance: interrupt + +ad_ip_instance axi_intc axi_intc +ad_ip_parameter axi_intc CONFIG.C_HAS_FAST 0 + +ad_ip_instance xlconcat sys_concat_intc +ad_ip_parameter sys_concat_intc CONFIG.NUM_PORTS 16 + +# ddr4 + +ad_connect sys_rst axi_ddr_cntrl/sys_rst +ad_connect sys_clk axi_ddr_cntrl/C0_SYS_CLK +ad_connect ddr4 axi_ddr_cntrl/C0_DDR4 +ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst axi_ddr_cntrl_rstgen/ext_reset_in +ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst sys_rstgen/ext_reset_in +ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst sys_250m_rstgen/ext_reset_in +ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst sys_500m_rstgen/ext_reset_in +ad_connect sys_mem_clk axi_ddr_cntrl/c0_ddr4_ui_clk +ad_connect sys_mem_clk axi_ddr_cntrl_rstgen/slowest_sync_clk +ad_connect sys_cpu_clk axi_ddr_cntrl/addn_ui_clkout1 +ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk +ad_connect sys_mem_resetn axi_ddr_cntrl_rstgen/peripheral_aresetn +ad_connect sys_mem_resetn axi_ddr_cntrl/c0_ddr4_aresetn +ad_connect sys_250m_clk axi_ddr_cntrl/addn_ui_clkout2 +ad_connect sys_250m_clk sys_250m_rstgen/slowest_sync_clk +ad_connect sys_500m_clk axi_ddr_cntrl/addn_ui_clkout3 +ad_connect sys_500m_clk sys_500m_rstgen/slowest_sync_clk +ad_connect sys_cpu_reset sys_rstgen/peripheral_reset +ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn +ad_connect sys_250m_reset sys_250m_rstgen/peripheral_reset +ad_connect sys_250m_resetn sys_250m_rstgen/peripheral_aresetn +ad_connect sys_500m_reset sys_500m_rstgen/peripheral_reset +ad_connect sys_500m_resetn sys_500m_rstgen/peripheral_aresetn + +# generic system clocks pointers + +set sys_cpu_clk [get_bd_pins axi_ddr_cntrl/addn_ui_clkout1] +set sys_dma_clk [get_bd_nets sys_250m_clk] +set sys_iodelay_clk [get_bd_nets sys_500m_clk] + +set sys_cpu_reset [get_bd_nets sys_cpu_reset] +set sys_cpu_resetn [get_bd_pins sys_rstgen/peripheral_aresetn] +set sys_dma_reset [get_bd_nets sys_250m_reset] +set sys_dma_resetn [get_bd_nets sys_250m_resetn] +set sys_iodelay_reset [get_bd_nets sys_500m_reset] +set sys_iodelay_resetn [get_bd_nets sys_500m_resetn] + +# microblaze debug & interrupt + +ad_connect sys_cpu_clk sys_mb/Clk +ad_connect sys_cpu_clk sys_dlmb/LMB_Clk +ad_connect sys_cpu_clk sys_ilmb/LMB_Clk +ad_connect sys_cpu_clk sys_dlmb_cntlr/LMB_Clk +ad_connect sys_cpu_clk sys_ilmb_cntlr/LMB_Clk +ad_connect sys_rstgen/mb_reset sys_mb/Reset +ad_connect sys_rstgen/bus_struct_reset sys_dlmb/SYS_Rst +ad_connect sys_rstgen/bus_struct_reset sys_ilmb/SYS_Rst +ad_connect sys_rstgen/bus_struct_reset sys_dlmb_cntlr/LMB_Rst +ad_connect sys_rstgen/bus_struct_reset sys_ilmb_cntlr/LMB_Rst +ad_connect sys_mb/DLMB sys_dlmb/LMB_M +ad_connect sys_mb/ILMB sys_ilmb/LMB_M +ad_connect sys_dlmb/LMB_Sl_0 sys_dlmb_cntlr/SLMB +ad_connect sys_ilmb/LMB_Sl_0 sys_ilmb_cntlr/SLMB +ad_connect sys_dlmb_cntlr/BRAM_PORT sys_lmb_bram/BRAM_PORTA +ad_connect sys_ilmb_cntlr/BRAM_PORT sys_lmb_bram/BRAM_PORTB +ad_connect sys_mb_debug/Debug_SYS_Rst sys_rstgen/mb_debug_sys_rst +ad_connect sys_mb_debug/MBDEBUG_0 sys_mb/DEBUG +ad_connect axi_intc/interrupt sys_mb/INTERRUPT +ad_connect axi_intc/intr sys_concat_intc/dout + +# ethernet + +ad_connect sgmii axi_ethernet_0/sgmii +ad_connect sgmii_phyclk axi_ethernet_0/lvds_clk +ad_connect mdio axi_ethernet_0/mdio +ad_connect phy_sd axi_ethernet_0/signal_detect +ad_connect phy_dummy_port_in axi_ethernet_0/dummy_port_in +ad_connect sys_cpu_clk axi_ethernet_0/axis_clk +ad_connect axi_ethernet_0/s_axis_txd axi_ethernet_dma/M_AXIS_MM2S +ad_connect axi_ethernet_0/s_axis_txc axi_ethernet_dma/M_AXIS_CNTRL +ad_connect axi_ethernet_0/m_axis_rxd axi_ethernet_dma/S_AXIS_S2MM +ad_connect axi_ethernet_0/m_axis_rxs axi_ethernet_dma/S_AXIS_STS +ad_connect axi_ethernet_0/axi_txd_arstn axi_ethernet_dma/mm2s_prmry_reset_out_n +ad_connect axi_ethernet_0/axi_txc_arstn axi_ethernet_dma/mm2s_cntrl_reset_out_n +ad_connect axi_ethernet_0/axi_rxd_arstn axi_ethernet_dma/s2mm_prmry_reset_out_n +ad_connect axi_ethernet_0/axi_rxs_arstn axi_ethernet_dma/s2mm_sts_reset_out_n + +# system id + +ad_ip_instance axi_sysid axi_sysid_0 +ad_ip_instance sysid_rom rom_sys_0 + +ad_connect axi_sysid_0/rom_addr rom_sys_0/rom_addr +ad_connect axi_sysid_0/sys_rom_data rom_sys_0/rom_data +ad_connect sys_cpu_clk rom_sys_0/clk + +# iic, spi and gpio + +ad_connect iic_main axi_iic_main/iic +ad_connect uart_sin axi_uart/rx +ad_connect uart_sout axi_uart/tx +ad_connect spi_csn_i axi_spi/ss_i +ad_connect spi_csn_o axi_spi/ss_o +ad_connect spi_clk_i axi_spi/sck_i +ad_connect spi_clk_o axi_spi/sck_o +ad_connect spi_sdo_i axi_spi/io0_i +ad_connect spi_sdo_o axi_spi/io0_o +ad_connect spi_sdi_i axi_spi/io1_i +ad_connect gpio0_i axi_gpio/gpio_io_i +ad_connect gpio0_o axi_gpio/gpio_io_o +ad_connect gpio0_t axi_gpio/gpio_io_t +ad_connect gpio1_i axi_gpio/gpio2_io_i +ad_connect gpio1_o axi_gpio/gpio2_io_o +ad_connect gpio1_t axi_gpio/gpio2_io_t +ad_connect sys_cpu_clk axi_spi/ext_spi_clk + +# defaults (interrupts) + +ad_connect sys_concat_intc/In0 axi_timer/interrupt +ad_connect sys_concat_intc/In1 axi_ethernet_0/interrupt +ad_connect sys_concat_intc/In2 axi_ethernet_dma/mm2s_introut +ad_connect sys_concat_intc/In3 axi_ethernet_dma/s2mm_introut +ad_connect sys_concat_intc/In4 axi_uart/interrupt +ad_connect sys_concat_intc/In5 GND +ad_connect sys_concat_intc/In6 GND +ad_connect sys_concat_intc/In7 GND +ad_connect sys_concat_intc/In8 GND +ad_connect sys_concat_intc/In9 axi_iic_main/iic2intc_irpt +ad_connect sys_concat_intc/In10 axi_spi/ip2intc_irpt +ad_connect sys_concat_intc/In11 axi_gpio/ip2intc_irpt +ad_connect sys_concat_intc/In12 GND +ad_connect sys_concat_intc/In13 GND +ad_connect sys_concat_intc/In14 GND +ad_connect sys_concat_intc/In15 GND + +# interconnect - processor + +ad_cpu_interconnect 0x40C00000 axi_ethernet_0 +ad_cpu_interconnect 0x41E10000 axi_ethernet_dma +ad_cpu_interconnect 0x40000000 axi_gpio +ad_cpu_interconnect 0x40600000 axi_uart +ad_cpu_interconnect 0x41200000 axi_intc +ad_cpu_interconnect 0x41C00000 axi_timer +ad_cpu_interconnect 0x41600000 axi_iic_main +ad_cpu_interconnect 0x45000000 axi_sysid_0 +ad_cpu_interconnect 0x44A70000 axi_spi +ad_cpu_interconnect 0x41400000 sys_mb_debug +ad_cpu_interconnect 0x45100000 axi_ddr_cntrl C0_DDR4_S_AXI_CTRL + +### Workaround for DDR controller with control interface +### DDR contoller control interface runs at UI clock not CPU clock +set_property -dict [list CONFIG.NUM_CLKS {2}] [get_bd_cells axi_cpu_interconnect] +ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk axi_cpu_interconnect/aclk1 + +# interconnect - memory + +ad_mem_hp0_interconnect sys_mem_clk axi_ddr_cntrl/C0_DDR4_S_AXI +ad_mem_hp0_interconnect sys_cpu_clk sys_mb/M_AXI_DC +ad_mem_hp0_interconnect sys_cpu_clk sys_mb/M_AXI_IC +ad_mem_hp0_interconnect sys_cpu_clk axi_ethernet_dma/M_AXI_SG +ad_mem_hp0_interconnect sys_cpu_clk axi_ethernet_dma/M_AXI_MM2S +ad_mem_hp0_interconnect sys_cpu_clk axi_ethernet_dma/M_AXI_S2MM + +create_bd_addr_seg -range 0x80000 -offset 0x0 [get_bd_addr_spaces sys_mb/Data] \ + [get_bd_addr_segs sys_dlmb_cntlr/SLMB/Mem] SEG_dlmb_cntlr +create_bd_addr_seg -range 0x80000 -offset 0x0 [get_bd_addr_spaces sys_mb/Instruction] \ + [get_bd_addr_segs sys_ilmb_cntlr/SLMB/Mem] SEG_ilmb_cntlr + diff --git a/projects/common/vcu128/vcu128_system_constr.xdc b/projects/common/vcu128/vcu128_system_constr.xdc new file mode 100644 index 000000000..8e17fa43a --- /dev/null +++ b/projects/common/vcu128/vcu128_system_constr.xdc @@ -0,0 +1,59 @@ + +# constraints + +set_property -dict {PACKAGE_PIN BM29 IOSTANDARD LVCMOS12} [get_ports sys_rst] + +# clocks +# DDR4 Component Memory I/F clock, fixed 100 MHz LVDS [U76] + +set_property -dict {PACKAGE_PIN BH51 IOSTANDARD LVDS} [get_ports sys_clk_p] +set_property -dict {PACKAGE_PIN BJ51 IOSTANDARD LVDS} [get_ports sys_clk_n] + +# ethernet + +set_property PACKAGE_PIN BG22 [get_ports phy_tx_p] +set_property PACKAGE_PIN BH22 [get_ports phy_tx_n] +set_property PACKAGE_PIN BJ22 [get_ports phy_rx_p] +set_property PACKAGE_PIN BK21 [get_ports phy_rx_n] + +set_property -dict {PACKAGE_PIN BH27 IOSTANDARD LVDS} [get_ports phy_clk_p] +set_property -dict {PACKAGE_PIN BJ27 IOSTANDARD LVDS} [get_ports phy_clk_n] + +set_property -dict {PACKAGE_PIN BN27 IOSTANDARD LVCMOS18} [get_ports mdio_mdc] +set_property -dict {PACKAGE_PIN BG23 IOSTANDARD LVCMOS18} [get_ports mdio_mdio] + +# uart + +set_property -dict {PACKAGE_PIN BP26 IOSTANDARD LVCMOS18} [get_ports uart_sin] +set_property -dict {PACKAGE_PIN BN26 IOSTANDARD LVCMOS18} [get_ports uart_sout] + +set_property -dict {PACKAGE_PIN BH24 IOSTANDARD LVCMOS18} [get_ports gpio_bd[0]] ; ## GPIO_LED_0_LS +set_property -dict {PACKAGE_PIN BG24 IOSTANDARD LVCMOS18} [get_ports gpio_bd[1]] ; ## GPIO_LED_1_LS +set_property -dict {PACKAGE_PIN BG25 IOSTANDARD LVCMOS18} [get_ports gpio_bd[2]] ; ## GPIO_LED_2_LS +set_property -dict {PACKAGE_PIN BF25 IOSTANDARD LVCMOS18} [get_ports gpio_bd[3]] ; ## GPIO_LED_3_LS +set_property -dict {PACKAGE_PIN BF26 IOSTANDARD LVCMOS18} [get_ports gpio_bd[4]] ; ## GPIO_LED_4_LS +set_property -dict {PACKAGE_PIN BF27 IOSTANDARD LVCMOS18} [get_ports gpio_bd[5]] ; ## GPIO_LED_5_LS +set_property -dict {PACKAGE_PIN BG27 IOSTANDARD LVCMOS18} [get_ports gpio_bd[6]] ; ## GPIO_LED_6_LS +set_property -dict {PACKAGE_PIN BG28 IOSTANDARD LVCMOS18} [get_ports gpio_bd[7]] ; ## GPIO_LED_7_LS + +# iic + +set_property -dict {PACKAGE_PIN BM27 IOSTANDARD LVCMOS18 DRIVE 8 SLEW SLOW} [get_ports iic_scl] +set_property -dict {PACKAGE_PIN BL28 IOSTANDARD LVCMOS18 DRIVE 8 SLEW SLOW} [get_ports iic_sda] + +# Create SPI clock +create_generated_clock -name spi_clk \ + -source [get_pins i_system_wrapper/system_i/axi_spi/ext_spi_clk] \ + -divide_by 2 [get_pins i_system_wrapper/system_i/axi_spi/sck_o] + +# Balance clocks +# +# Minimize skew on synchronous CDC timing paths between clocks originating +# from the same MMCM source. (sys_mem_clk and sys_cpu_clk) +# This is required mostly by the smart interconnect. +# Property must be applied directly to the output net of BUFGs. +set_property CLOCK_DELAY_GROUP BALANCE_CLOCKS \ + [list [get_nets [get_property PARENT [get_nets {i_system_wrapper/system_i/sys_cpu_clk}]]] \ + [get_nets [get_property PARENT [get_nets {i_system_wrapper/system_i/sys_mem_clk}]]] \ + ] + diff --git a/projects/scripts/adi_project_xilinx.tcl b/projects/scripts/adi_project_xilinx.tcl index 2525a8fb8..ae1f78e4e 100644 --- a/projects/scripts/adi_project_xilinx.tcl +++ b/projects/scripts/adi_project_xilinx.tcl @@ -56,7 +56,7 @@ set p_prcfg_status "" # \param[parameter_list] - a list of global parameters (parameters of the # system_top module) # -# Supported carrier names are: ac701, kc705, vc707, vcu118, kcu105, zed, +# Supported carrier names are: ac701, kc705, vc707, vcu118, vcu128, kcu105, zed, # microzed, zc702, zc706, mitx405, zcu102. # proc adi_project {project_name {mode 0} {parameter_list {}} } { @@ -81,6 +81,10 @@ proc adi_project {project_name {mode 0} {parameter_list {}} } { set device "xcvu9p-flga2104-2L-e" set board [lindex [lsearch -all -inline [get_board_parts] *vcu118*] end] } + if [regexp "_vcu128$" $project_name] { + set device "xcvu37p-fsvh2892-2L-e" + set board [lindex [lsearch -all -inline [get_board_parts] *vcu128:part0*] end] + } if [regexp "_kcu105$" $project_name] { set device "xcku040-ffva1156-2-e" set board [lindex [lsearch -all -inline [get_board_parts] *kcu105*] end]