ad719x_asdz/coraz7s: Initial commit
* Added interrupt on RDYn on GPIO 32 Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>main
Iulia Moldovan
imoldovan
parent
19c76d1d4f
commit
880f37555f
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####################################################################################
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## Copyright (c) 2018 - 2021 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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include ../scripts/project-toplevel.mk
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# EVAL-AD719X-ASDZ HDL Project
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This project supports EVAL-AD7190, EVAL-AD7193 and EVAL-AD7195.
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Here are some pointers to help you:
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* [EVAL-AD7190 Board Product Page](https://www.analog.com/eval-ad7190)
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* [EVAL-AD7193 Board Product Page](https://www.analog.com/eval-ad7193)
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* [EVAL-AD7195 Board Product Page](https://www.analog.com/eval-ad7195)
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* Parts: AD7190 [Sigma-Delta ADC, SPI interface, 24-bit resolution, Data rate between 4.7Hz - 4.8kHz](https://www.analog.com/ad7190)
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* Parts: AD7193 [4-channel Sigma-Delta ADC, SPI interface, 24-bit resolution, Data rate between 4.7Hz - 4.8kHz](https://www.analog.com/ad7193)
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* Parts: AD7195 [Sigma-Delta ADC, SPI interface, 24-bit resolution, Data rate between 4.7Hz - 4.8kHz](https://www.analog.com/ad7195)
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* Project Doc: https://wiki.analog.com/resources/eval/adc/ad719x_asdz
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* HDL Doc: https://wiki.analog.com/resources/eval/adc/ad719x_asdz
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* Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers-all
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####################################################################################
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## Copyright (c) 2018 - 2021 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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PROJECT_NAME := ad719x_asdz_coraz7s
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M_DEPS += ../../scripts/adi_pd.tcl
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M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl
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M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc
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M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl
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M_DEPS += ../../../library/common/ad_iobuf.v
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LIB_DEPS += axi_sysid
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LIB_DEPS += sysid_rom
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include ../../scripts/project-xilinx.mk
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source $ad_hdl_dir/projects/common/coraz7s/coraz7s_system_bd.tcl
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source $ad_hdl_dir/projects/scripts/adi_pd.tcl
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# system ID
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ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
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ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
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ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
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set sys_cstring "sys rom custom string placeholder"
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sysid_gen_sys_init_file
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# coraz7s
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# ad719x spi connections
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set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS33} [get_ports {adc_spi_sclk}]; # IO_L7N_T1_34 Sch=ja_n[2]
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set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33} [get_ports {adc_spi_miso_rdyn}]; # IO_L7P_T1_34 Sch=ja_p[2]; AD719X sch=DOUT/RDY_N
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set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports {adc_spi_mosi}]; # IO_L17N_T2_34 Sch=ja_n[1]; AD719X sch=DIN
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set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33} [get_ports {adc_spi_csn}]; # IO_L17P_T2_34 Sch=ja_p[1]
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source ../../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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adi_project ad719x_asdz_coraz7s
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adi_project_files ad719x_asdz_coraz7s [list \
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"$ad_hdl_dir/library/common/ad_iobuf.v" \
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"$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc" \
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"system_constr.xdc" \
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"system_top.v"
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]
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adi_project_run ad719x_asdz_coraz7s
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@ -0,0 +1,155 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2022 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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inout [14:0] ddr_addr,
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inout [ 2:0] ddr_ba,
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inout ddr_cas_n,
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inout ddr_ck_n,
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inout ddr_ck_p,
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inout ddr_cke,
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inout ddr_cs_n,
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inout [ 3:0] ddr_dm,
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inout [31:0] ddr_dq,
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inout [ 3:0] ddr_dqs_n,
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inout [ 3:0] ddr_dqs_p,
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inout ddr_odt,
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inout ddr_ras_n,
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inout ddr_reset_n,
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inout ddr_we_n,
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inout fixed_io_ddr_vrn,
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inout fixed_io_ddr_vrp,
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inout [53:0] fixed_io_mio,
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inout fixed_io_ps_clk,
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inout fixed_io_ps_porb,
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inout fixed_io_ps_srstb,
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inout [ 1:0] btn,
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inout [ 5:0] led,
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// ad7190 spi pins
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output adc_spi_sclk,
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input adc_spi_miso_rdyn,
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output adc_spi_mosi,
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output adc_spi_csn
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);
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// internal signals
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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// instantiations
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ad_iobuf #(
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.DATA_WIDTH (2)
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) i_iobuf_buttons (
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.dio_t (gpio_t[1:0]),
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.dio_i (gpio_o[1:0]),
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.dio_o (gpio_i[1:0]),
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.dio_p (btn));
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ad_iobuf #(
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.DATA_WIDTH (6)
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) i_iobuf_leds (
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.dio_t (gpio_t[7:2]),
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.dio_i (gpio_o[7:2]),
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.dio_o (gpio_i[7:2]),
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.dio_p (led));
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// project specific gpios
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assign gpio_i[63:33] = gpio_o[63:33];
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assign gpio_i[32] = adc_spi_miso_rdyn;
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// board specific gpios
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assign gpio_i[31:8] = gpio_o[31:8];
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system_wrapper i_system_wrapper (
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.ddr_addr (ddr_addr),
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.ddr_ba (ddr_ba),
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.ddr_cas_n (ddr_cas_n),
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.ddr_ck_n (ddr_ck_n),
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.ddr_ck_p (ddr_ck_p),
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.ddr_cke (ddr_cke),
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.ddr_cs_n (ddr_cs_n),
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.ddr_dm (ddr_dm),
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.ddr_dq (ddr_dq),
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.ddr_dqs_n (ddr_dqs_n),
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.ddr_dqs_p (ddr_dqs_p),
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.ddr_odt (ddr_odt),
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.ddr_ras_n (ddr_ras_n),
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.ddr_reset_n (ddr_reset_n),
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.ddr_we_n (ddr_we_n),
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.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
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.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
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.fixed_io_mio (fixed_io_mio),
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.fixed_io_ps_clk (fixed_io_ps_clk),
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.fixed_io_ps_porb (fixed_io_ps_porb),
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.fixed_io_ps_srstb (fixed_io_ps_srstb),
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.spi0_clk_i (1'b0),
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.spi0_clk_o (adc_spi_sclk),
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.spi0_csn_0_o (adc_spi_csn),
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.spi0_csn_1_o (),
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.spi0_csn_2_o (),
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.spi0_csn_i (1'b0),
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.spi0_sdi_i (adc_spi_miso_rdyn),
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.spi0_sdo_i (1'b0),
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.spi0_sdo_o (adc_spi_mosi),
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.spi1_clk_i (1'b0),
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.spi1_clk_o (),
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.spi1_csn_0_o (),
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.spi1_csn_1_o (),
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.spi1_csn_2_o (),
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.spi1_csn_i (1'b1),
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.spi1_sdi_i (1'b0),
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.spi1_sdo_i (1'b0),
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.spi1_sdo_o ());
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endmodule
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