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common- adc- data path disable split

main
Rejeesh Kutty 2016-09-23 13:40:35 -04:00
parent 78f7384150
commit 8729af1b91
5 changed files with 560 additions and 467 deletions
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81
library/common/ad_datafmt.v
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@ -34,72 +34,73 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// data format (offset binary or 2's complement only) // data format (offset binary or 2's complement only)
`timescale 1ps/1ps `timescale 1ps/1ps
module ad_datafmt ( module ad_datafmt #(
// data bus width
parameter DATA_WIDTH = 16,
parameter DISABLE = 0) (
// data path // data path
clk, input clk,
valid, input valid,
data, input [(DATA_WIDTH-1):0] data,
valid_out, output valid_out,
data_out, output [15:0] data_out,
// control signals // control signals
dfmt_enable, input dfmt_enable,
dfmt_type, input dfmt_type,
dfmt_se); input dfmt_se);
// delayed data bus width
parameter DATA_WIDTH = 16;
localparam DW = DATA_WIDTH - 1;
// data path
input clk;
input valid;
input [DW:0] data;
output valid_out;
output [15:0] data_out;
// control signals
input dfmt_enable;
input dfmt_type;
input dfmt_se;
// internal registers // internal registers
reg valid_out = 'd0; reg valid_int = 'd0;
reg [15:0] data_out = 'd0; reg [15:0] data_int = 'd0;
// internal signals // internal signals
wire type_s; wire type_s;
wire signext_s; wire signext_s;
wire [DW:0] data_s; wire sign_s;
wire [23:0] sign_s; wire [15:0] data_out_s;
wire [23:0] data_out_s;
// data-path disable
generate
if (DISABLE == 1) begin
assign valid_out = valid;
assign data_out = data;
end else begin
assign valid_out = valid_int;
assign data_out = data_int;
end
endgenerate
// if offset-binary convert to 2's complement first // if offset-binary convert to 2's complement first
assign type_s = dfmt_enable & dfmt_type; assign type_s = dfmt_enable & dfmt_type;
assign signext_s = dfmt_enable & dfmt_se; assign signext_s = dfmt_enable & dfmt_se;
assign sign_s = signext_s & (type_s ^ data[(DATA_WIDTH-1)]);
assign data_s = (type_s == 1'b1) ? {~data[DW], data[(DW-1):0]} : data; generate
assign sign_s = (signext_s == 1'b1) ? {{24{data_s[DW]}}} : 24'd0; if (DATA_WIDTH < 16) begin
assign data_out_s = {sign_s[23:(DW+1)], data_s}; assign data_out_s[15:DATA_WIDTH] = {(16-DATA_WIDTH){sign_s}};
end
endgenerate
assign data_out_s[(DATA_WIDTH-1)] = type_s ^ data[(DATA_WIDTH-1)];
assign data_out_s[(DATA_WIDTH-2):0] = data[(DATA_WIDTH-2):0];
always @(posedge clk) begin always @(posedge clk) begin
valid_out <= valid; valid_int <= valid;
data_out <= data_out_s[15:0]; data_int <= data_out_s[15:0];
end end
endmodule endmodule

71
library/common/ad_dcfilter.v
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@ -34,44 +34,33 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// dc filter- y(n) = c*x(n) + (1-c)*y(n-1) // dc filter- y(n) = c*x(n) + (1-c)*y(n-1)
`timescale 1ps/1ps `timescale 1ps/1ps
module ad_dcfilter ( module ad_dcfilter #(
// data path disable
parameter DISABLE = 0) (
// data interface // data interface
clk, input clk,
valid, input valid,
data, input [15:0] data,
valid_out, output valid_out,
data_out, output [15:0] data_out,
// control interface // control interface
dcfilt_enb, input dcfilt_enb,
dcfilt_coeff, input [15:0] dcfilt_coeff,
dcfilt_offset); input [15:0] dcfilt_offset);
// data interface
input clk;
input valid;
input [15:0] data;
output valid_out;
output [15:0] data_out;
// control interface
input dcfilt_enb;
input [15:0] dcfilt_coeff;
input [15:0] dcfilt_offset;
// internal registers // internal registers
reg [15:0] dcfilt_coeff_d = 'd0;
reg [47:0] dc_offset = 'd0; reg [47:0] dc_offset = 'd0;
reg [47:0] dc_offset_d = 'd0; reg [47:0] dc_offset_d = 'd0;
reg valid_d = 'd0; reg valid_d = 'd0;
@ -79,21 +68,33 @@ module ad_dcfilter (
reg valid_2d = 'd0; reg valid_2d = 'd0;
reg [15:0] data_2d = 'd0; reg [15:0] data_2d = 'd0;
reg [15:0] data_dcfilt = 'd0; reg [15:0] data_dcfilt = 'd0;
reg valid_out = 'd0; reg valid_int = 'd0;
reg [15:0] data_out = 'd0; reg [15:0] data_int = 'd0;
reg [15:0] dcfilt_coeff_r;
// internal signals // internal signals
wire [47:0] dc_offset_s; wire [47:0] dc_offset_s;
// cancelling the dc offset // data-path disable
generate
if (DISABLE == 1) begin
assign valid_out = valid;
assign data_out = data;
end else begin
assign valid_out = valid_int;
assign data_out = data_int;
end
endgenerate
// dcfilt_coeff is flopped so to remove warnings from vivado // dcfilt_coeff is flopped so to remove warnings from vivado
always @(posedge clk) begin always @(posedge clk) begin
dcfilt_coeff_r <= dcfilt_coeff; dcfilt_coeff_d <= dcfilt_coeff;
end end
// removing dc offset
always @(posedge clk) begin always @(posedge clk) begin
dc_offset <= dc_offset_s; dc_offset <= dc_offset_s;
dc_offset_d <= dc_offset; dc_offset_d <= dc_offset;
@ -105,11 +106,11 @@ module ad_dcfilter (
data_2d <= data_d; data_2d <= data_d;
data_dcfilt <= data_d - dc_offset[32:17]; data_dcfilt <= data_d - dc_offset[32:17];
if (dcfilt_enb == 1'b1) begin if (dcfilt_enb == 1'b1) begin
valid_out <= valid_2d; valid_int <= valid_2d;
data_out <= data_dcfilt; data_int <= data_dcfilt;
end else begin end else begin
valid_out <= valid_2d; valid_int <= valid_2d;
data_out <= data_2d; data_int <= data_2d;
end end
end end
@ -144,7 +145,7 @@ module ad_dcfilter (
i_dsp48e1 ( i_dsp48e1 (
.CLK (clk), .CLK (clk),
.A ({{14{dc_offset_s[32]}}, dc_offset_s[32:17]}), .A ({{14{dc_offset_s[32]}}, dc_offset_s[32:17]}),
.B ({{2{dcfilt_coeff_r[15]}}, dcfilt_coeff_r}), .B ({{2{dcfilt_coeff_d[15]}}, dcfilt_coeff_d}),
.C (dc_offset_d), .C (dc_offset_d),
.D ({{9{data_d[15]}}, data_d}), .D ({{9{data_d[15]}}, data_d}),
.MULTSIGNIN (1'd0), .MULTSIGNIN (1'd0),

62
library/common/ad_iqcor.v
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@ -38,41 +38,27 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module ad_iqcor ( module ad_iqcor #(
// data interface
clk,
valid,
data_in,
data_iq,
valid_out,
data_out,
// control interface
iqcor_enable,
iqcor_coeff_1,
iqcor_coeff_2);
// select i/q if disabled // select i/q if disabled
parameter Q_OR_I_N = 0; parameter Q_OR_I_N = 0,
parameter DISABLE = 0) (
// data interface // data interface
input clk; input clk,
input valid; input valid,
input [15:0] data_in; input [15:0] data_in,
input [15:0] data_iq; input [15:0] data_iq,
output valid_out; output valid_out,
output [15:0] data_out; output [15:0] data_out,
// control interface // control interface
input iqcor_enable; input iqcor_enable,
input [15:0] iqcor_coeff_1; input [15:0] iqcor_coeff_1,
input [15:0] iqcor_coeff_2; input [15:0] iqcor_coeff_2);
// internal registers // internal registers
@ -80,8 +66,8 @@ module ad_iqcor (
reg [15:0] p1_data_i = 'd0; reg [15:0] p1_data_i = 'd0;
reg [15:0] p1_data_q = 'd0; reg [15:0] p1_data_q = 'd0;
reg [33:0] p1_data_p = 'd0; reg [33:0] p1_data_p = 'd0;
reg valid_out = 'd0; reg valid_int = 'd0;
reg [15:0] data_out = 'd0; reg [15:0] data_int = 'd0;
reg [15:0] iqcor_coeff_1_r = 'd0; reg [15:0] iqcor_coeff_1_r = 'd0;
reg [15:0] iqcor_coeff_2_r = 'd0; reg [15:0] iqcor_coeff_2_r = 'd0;
@ -95,6 +81,18 @@ module ad_iqcor (
wire [33:0] p1_data_p_q_s; wire [33:0] p1_data_p_q_s;
wire [15:0] p1_data_q_s; wire [15:0] p1_data_q_s;
// data-path disable
generate
if (DISABLE == 1) begin
assign valid_out = valid;
assign data_out = data_in;
end else begin
assign valid_out = valid_int;
assign data_out = data_int;
end
endgenerate
// swap i & q // swap i & q
assign data_i_s = (Q_OR_I_N == 1) ? data_iq : data_in; assign data_i_s = (Q_OR_I_N == 1) ? data_iq : data_in;
@ -139,13 +137,13 @@ module ad_iqcor (
// output registers // output registers
always @(posedge clk) begin always @(posedge clk) begin
valid_out <= p1_valid; valid_int <= p1_valid;
if (iqcor_enable == 1'b1) begin if (iqcor_enable == 1'b1) begin
data_out <= p1_data_p[29:14]; data_int <= p1_data_p[29:14];
end else if (Q_OR_I_N == 1) begin end else if (Q_OR_I_N == 1) begin
data_out <= p1_data_q; data_int <= p1_data_q;
end else begin end else begin
data_out <= p1_data_i; data_int <= p1_data_i;
end end
end end

415
library/common/up_adc_channel.v
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@ -34,127 +34,76 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps `timescale 1ns/100ps
module up_adc_channel ( module up_adc_channel #(
// adc interface
adc_clk,
adc_rst,
adc_enable,
adc_iqcor_enb,
adc_dcfilt_enb,
adc_dfmt_se,
adc_dfmt_type,
adc_dfmt_enable,
adc_dcfilt_offset,
adc_dcfilt_coeff,
adc_iqcor_coeff_1,
adc_iqcor_coeff_2,
adc_pnseq_sel,
adc_data_sel,
adc_pn_err,
adc_pn_oos,
adc_or,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
// user controls
up_usr_datatype_be,
up_usr_datatype_signed,
up_usr_datatype_shift,
up_usr_datatype_total_bits,
up_usr_datatype_bits,
up_usr_decimation_m,
up_usr_decimation_n,
adc_usr_datatype_be,
adc_usr_datatype_signed,
adc_usr_datatype_shift,
adc_usr_datatype_total_bits,
adc_usr_datatype_bits,
adc_usr_decimation_m,
adc_usr_decimation_n,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters // parameters
parameter ADC_COMMON_ID = 6'h01; parameter COMMON_ID = 6'h01,
parameter ADC_CHANNEL_ID = 4'h0; parameter CHANNEL_ID = 4'h0,
parameter USERPORTS_DISABLE = 0,
parameter DATAFORMAT_DISABLE = 0,
parameter DCFILTER_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 0) (
// adc interface // adc interface
input adc_clk; input adc_clk,
input adc_rst; input adc_rst,
output adc_enable; output adc_enable,
output adc_iqcor_enb; output adc_iqcor_enb,
output adc_dcfilt_enb; output adc_dcfilt_enb,
output adc_dfmt_se; output adc_dfmt_se,
output adc_dfmt_type; output adc_dfmt_type,
output adc_dfmt_enable; output adc_dfmt_enable,
output [15:0] adc_dcfilt_offset; output [15:0] adc_dcfilt_offset,
output [15:0] adc_dcfilt_coeff; output [15:0] adc_dcfilt_coeff,
output [15:0] adc_iqcor_coeff_1; output [15:0] adc_iqcor_coeff_1,
output [15:0] adc_iqcor_coeff_2; output [15:0] adc_iqcor_coeff_2,
output [ 3:0] adc_pnseq_sel; output [ 3:0] adc_pnseq_sel,
output [ 3:0] adc_data_sel; output [ 3:0] adc_data_sel,
input adc_pn_err; input adc_pn_err,
input adc_pn_oos; input adc_pn_oos,
input adc_or; input adc_or,
output up_adc_pn_err; output up_adc_pn_err,
output up_adc_pn_oos; output up_adc_pn_oos,
output up_adc_or; output up_adc_or,
// user controls // user controls
output up_usr_datatype_be; output up_usr_datatype_be,
output up_usr_datatype_signed; output up_usr_datatype_signed,
output [ 7:0] up_usr_datatype_shift; output [ 7:0] up_usr_datatype_shift,
output [ 7:0] up_usr_datatype_total_bits; output [ 7:0] up_usr_datatype_total_bits,
output [ 7:0] up_usr_datatype_bits; output [ 7:0] up_usr_datatype_bits,
output [15:0] up_usr_decimation_m; output [15:0] up_usr_decimation_m,
output [15:0] up_usr_decimation_n; output [15:0] up_usr_decimation_n,
input adc_usr_datatype_be; input adc_usr_datatype_be,
input adc_usr_datatype_signed; input adc_usr_datatype_signed,
input [ 7:0] adc_usr_datatype_shift; input [ 7:0] adc_usr_datatype_shift,
input [ 7:0] adc_usr_datatype_total_bits; input [ 7:0] adc_usr_datatype_total_bits,
input [ 7:0] adc_usr_datatype_bits; input [ 7:0] adc_usr_datatype_bits,
input [15:0] adc_usr_decimation_m; input [15:0] adc_usr_decimation_m,
input [15:0] adc_usr_decimation_n; input [15:0] adc_usr_decimation_n,
// bus interface // bus interface
input up_rstn; input up_rstn,
input up_clk; input up_clk,
input up_wreq; input up_wreq,
input [13:0] up_waddr; input [13:0] up_waddr,
input [31:0] up_wdata; input [31:0] up_wdata,
output up_wack; output up_wack,
input up_rreq; input up_rreq,
input [13:0] up_raddr; input [13:0] up_raddr,
output [31:0] up_rdata; output [31:0] up_rdata,
output up_rack; output up_rack);
// internal registers // internal registers
reg up_wack = 'd0; reg up_wack_int = 'd0;
reg up_adc_lb_enb = 'd0; reg up_adc_lb_enb = 'd0;
reg up_adc_pn_sel = 'd0; reg up_adc_pn_sel = 'd0;
reg up_adc_iqcor_enb = 'd0; reg up_adc_iqcor_enb = 'd0;
@ -164,24 +113,24 @@ module up_adc_channel (
reg up_adc_dfmt_enable = 'd0; reg up_adc_dfmt_enable = 'd0;
reg up_adc_pn_type = 'd0; reg up_adc_pn_type = 'd0;
reg up_adc_enable = 'd0; reg up_adc_enable = 'd0;
reg up_adc_pn_err = 'd0; reg up_adc_pn_err_int = 'd0;
reg up_adc_pn_oos = 'd0; reg up_adc_pn_oos_int = 'd0;
reg up_adc_or = 'd0; reg up_adc_or_int = 'd0;
reg [15:0] up_adc_dcfilt_offset = 'd0; reg [15:0] up_adc_dcfilt_offset = 'd0;
reg [15:0] up_adc_dcfilt_coeff = 'd0; reg [15:0] up_adc_dcfilt_coeff = 'd0;
reg [15:0] up_adc_iqcor_coeff_1 = 'd0; reg [15:0] up_adc_iqcor_coeff_1 = 'd0;
reg [15:0] up_adc_iqcor_coeff_2 = 'd0; reg [15:0] up_adc_iqcor_coeff_2 = 'd0;
reg [ 3:0] up_adc_pnseq_sel = 'd0; reg [ 3:0] up_adc_pnseq_sel = 'd0;
reg [ 3:0] up_adc_data_sel = 'd0; reg [ 3:0] up_adc_data_sel = 'd0;
reg up_usr_datatype_be = 'd0; reg up_usr_datatype_be_int = 'd0;
reg up_usr_datatype_signed = 'd0; reg up_usr_datatype_signed_int = 'd0;
reg [ 7:0] up_usr_datatype_shift = 'd0; reg [ 7:0] up_usr_datatype_shift_int = 'd0;
reg [ 7:0] up_usr_datatype_total_bits = 'd0; reg [ 7:0] up_usr_datatype_total_bits_int = 'd0;
reg [ 7:0] up_usr_datatype_bits = 'd0; reg [ 7:0] up_usr_datatype_bits_int = 'd0;
reg [15:0] up_usr_decimation_m = 'd0; reg [15:0] up_usr_decimation_m_int = 'd0;
reg [15:0] up_usr_decimation_n = 'd0; reg [15:0] up_usr_decimation_n_int = 'd0;
reg up_rack = 'd0; reg up_rack_int = 'd0;
reg [31:0] up_rdata = 'd0; reg [31:0] up_rdata_int = 'd0;
reg [15:0] up_adc_iqcor_coeff_tc_1 = 'd0; reg [15:0] up_adc_iqcor_coeff_tc_1 = 'd0;
reg [15:0] up_adc_iqcor_coeff_tc_2 = 'd0; reg [15:0] up_adc_iqcor_coeff_tc_2 = 'd0;
reg [ 3:0] up_adc_pnseq_sel_m = 'd0; reg [ 3:0] up_adc_pnseq_sel_m = 'd0;
@ -210,121 +159,253 @@ module up_adc_channel (
end end
endfunction endfunction
// up control/status
assign up_adc_pn_err = up_adc_pn_err_int;
assign up_adc_pn_oos = up_adc_pn_oos_int;
assign up_adc_or = up_adc_or_int;
assign up_usr_datatype_be = up_usr_datatype_be_int;
assign up_usr_datatype_signed = up_usr_datatype_signed_int;
assign up_usr_datatype_shift = up_usr_datatype_shift_int;
assign up_usr_datatype_total_bits = up_usr_datatype_total_bits_int;
assign up_usr_datatype_bits = up_usr_datatype_bits_int;
assign up_usr_decimation_m = up_usr_decimation_m_int;
assign up_usr_decimation_n = up_usr_decimation_n_int;
// decode block select // decode block select
assign up_wreq_s = ((up_waddr[13:8] == ADC_COMMON_ID) && (up_waddr[7:4] == ADC_CHANNEL_ID)) ? up_wreq : 1'b0; assign up_wreq_s = ((up_waddr[13:8] == COMMON_ID) && (up_waddr[7:4] == CHANNEL_ID)) ? up_wreq : 1'b0;
assign up_rreq_s = ((up_raddr[13:8] == ADC_COMMON_ID) && (up_raddr[7:4] == ADC_CHANNEL_ID)) ? up_rreq : 1'b0; assign up_rreq_s = ((up_raddr[13:8] == COMMON_ID) && (up_raddr[7:4] == CHANNEL_ID)) ? up_rreq : 1'b0;
// processor write interface // processor write interface
assign up_wack = up_wack_int;
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin if (up_rstn == 0) begin
up_wack <= 'd0; up_wack_int <= 'd0;
up_adc_lb_enb <= 'd0; up_adc_lb_enb <= 'd0;
up_adc_pn_sel <= 'd0; up_adc_pn_sel <= 'd0;
up_adc_iqcor_enb <= 'd0;
up_adc_dcfilt_enb <= 'd0;
up_adc_dfmt_se <= 'd0;
up_adc_dfmt_type <= 'd0;
up_adc_dfmt_enable <= 'd0;
up_adc_pn_type <= 'd0;
up_adc_enable <= 'd0;
up_adc_pn_err <= 'd0;
up_adc_pn_oos <= 'd0;
up_adc_or <= 'd0;
up_adc_dcfilt_offset <= 'd0;
up_adc_dcfilt_coeff <= 'd0;
up_adc_iqcor_coeff_1 <= 'd0;
up_adc_iqcor_coeff_2 <= 'd0;
up_adc_pnseq_sel <= 'd0;
up_adc_data_sel <= 'd0;
up_usr_datatype_be <= 'd0;
up_usr_datatype_signed <= 'd0;
up_usr_datatype_shift <= 'd0;
up_usr_datatype_total_bits <= 'd0;
up_usr_datatype_bits <= 'd0;
up_usr_decimation_m <= 'd0;
up_usr_decimation_n <= 'd0;
end else begin end else begin
up_wack <= up_wreq_s; up_wack_int <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
up_adc_lb_enb <= up_wdata[11]; up_adc_lb_enb <= up_wdata[11];
up_adc_pn_sel <= up_wdata[10]; up_adc_pn_sel <= up_wdata[10];
end
end
end
generate
if (IQCORRECTION_DISABLE == 1) begin
always @(posedge up_clk) begin
up_adc_iqcor_enb <= 'd0;
end
end else begin
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_adc_iqcor_enb <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
up_adc_iqcor_enb <= up_wdata[9]; up_adc_iqcor_enb <= up_wdata[9];
end
end
end
end
endgenerate
generate
if (DCFILTER_DISABLE == 1) begin
always @(posedge up_clk) begin
up_adc_dcfilt_enb <= 'd0;
end
end else begin
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_adc_dcfilt_enb <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
up_adc_dcfilt_enb <= up_wdata[8]; up_adc_dcfilt_enb <= up_wdata[8];
end
end
end
end
endgenerate
generate
if (DATAFORMAT_DISABLE == 1) begin
always @(posedge up_clk) begin
up_adc_dfmt_se <= 'd0;
up_adc_dfmt_type <= 'd0;
up_adc_dfmt_enable <= 'd0;
end
end else begin
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_adc_dfmt_se <= 'd0;
up_adc_dfmt_type <= 'd0;
up_adc_dfmt_enable <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
up_adc_dfmt_se <= up_wdata[6]; up_adc_dfmt_se <= up_wdata[6];
up_adc_dfmt_type <= up_wdata[5]; up_adc_dfmt_type <= up_wdata[5];
up_adc_dfmt_enable <= up_wdata[4]; up_adc_dfmt_enable <= up_wdata[4];
end
end
end
end
endgenerate
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_adc_pn_type <= 'd0;
up_adc_enable <= 'd0;
up_adc_pn_err_int <= 'd0;
up_adc_pn_oos_int <= 'd0;
up_adc_or_int <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
up_adc_pn_type <= up_wdata[1]; up_adc_pn_type <= up_wdata[1];
up_adc_enable <= up_wdata[0]; up_adc_enable <= up_wdata[0];
end end
if (up_adc_pn_err_s == 1'b1) begin if (up_adc_pn_err_s == 1'b1) begin
up_adc_pn_err <= 1'b1; up_adc_pn_err_int <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin
up_adc_pn_err <= up_adc_pn_err & ~up_wdata[2]; up_adc_pn_err_int <= up_adc_pn_err_int & ~up_wdata[2];
end end
if (up_adc_pn_oos_s == 1'b1) begin if (up_adc_pn_oos_s == 1'b1) begin
up_adc_pn_oos <= 1'b1; up_adc_pn_oos_int <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin
up_adc_pn_oos <= up_adc_pn_oos & ~up_wdata[1]; up_adc_pn_oos_int <= up_adc_pn_oos_int & ~up_wdata[1];
end end
if (up_adc_or_s == 1'b1) begin if (up_adc_or_s == 1'b1) begin
up_adc_or <= 1'b1; up_adc_or_int <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin
up_adc_or <= up_adc_or & ~up_wdata[0]; up_adc_or_int <= up_adc_or_int & ~up_wdata[0];
end end
end
end
generate
if (DCFILTER_DISABLE == 1) begin
always @(posedge up_clk) begin
up_adc_dcfilt_offset <= 'd0;
up_adc_dcfilt_coeff <= 'd0;
end
end else begin
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_adc_dcfilt_offset <= 'd0;
up_adc_dcfilt_coeff <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h4)) begin if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h4)) begin
up_adc_dcfilt_offset <= up_wdata[31:16]; up_adc_dcfilt_offset <= up_wdata[31:16];
up_adc_dcfilt_coeff <= up_wdata[15:0]; up_adc_dcfilt_coeff <= up_wdata[15:0];
end end
end
end
end
endgenerate
generate
if (IQCORRECTION_DISABLE == 1) begin
always @(posedge up_clk) begin
up_adc_iqcor_coeff_1 <= 'd0;
up_adc_iqcor_coeff_2 <= 'd0;
end
end else begin
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_adc_iqcor_coeff_1 <= 'd0;
up_adc_iqcor_coeff_2 <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h5)) begin if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h5)) begin
up_adc_iqcor_coeff_1 <= up_wdata[31:16]; up_adc_iqcor_coeff_1 <= up_wdata[31:16];
up_adc_iqcor_coeff_2 <= up_wdata[15:0]; up_adc_iqcor_coeff_2 <= up_wdata[15:0];
end end
end
end
end
endgenerate
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_adc_pnseq_sel <= 'd0;
up_adc_data_sel <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h6)) begin if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h6)) begin
up_adc_pnseq_sel <= up_wdata[19:16]; up_adc_pnseq_sel <= up_wdata[19:16];
up_adc_data_sel <= up_wdata[3:0]; up_adc_data_sel <= up_wdata[3:0];
end end
end
end
generate
if (USERPORTS_DISABLE == 1) begin
always @(posedge up_clk) begin
up_usr_datatype_be_int <= 'd0;
up_usr_datatype_signed_int <= 'd0;
up_usr_datatype_shift_int <= 'd0;
up_usr_datatype_total_bits_int <= 'd0;
up_usr_datatype_bits_int <= 'd0;
up_usr_decimation_m_int <= 'd0;
up_usr_decimation_n_int <= 'd0;
end
end else begin
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_usr_datatype_be_int <= 'd0;
up_usr_datatype_signed_int <= 'd0;
up_usr_datatype_shift_int <= 'd0;
up_usr_datatype_total_bits_int <= 'd0;
up_usr_datatype_bits_int <= 'd0;
up_usr_decimation_m_int <= 'd0;
up_usr_decimation_n_int <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h8)) begin if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h8)) begin
up_usr_datatype_be <= up_wdata[25]; up_usr_datatype_be_int <= up_wdata[25];
up_usr_datatype_signed <= up_wdata[24]; up_usr_datatype_signed_int <= up_wdata[24];
up_usr_datatype_shift <= up_wdata[23:16]; up_usr_datatype_shift_int <= up_wdata[23:16];
up_usr_datatype_total_bits <= up_wdata[15:8]; up_usr_datatype_total_bits_int <= up_wdata[15:8];
up_usr_datatype_bits <= up_wdata[7:0]; up_usr_datatype_bits_int <= up_wdata[7:0];
end end
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h9)) begin if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h9)) begin
up_usr_decimation_m <= up_wdata[31:16]; up_usr_decimation_m_int <= up_wdata[31:16];
up_usr_decimation_n <= up_wdata[15:0]; up_usr_decimation_n_int <= up_wdata[15:0];
end end
end end
end end
end
endgenerate
// processor read interface // processor read interface
assign up_rack = up_rack_int;
assign up_rdata = up_rdata_int;
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin if (up_rstn == 0) begin
up_rack <= 'd0; up_rack_int <= 'd0;
up_rdata <= 'd0; up_rdata_int <= 'd0;
end else begin end else begin
up_rack <= up_rreq_s; up_rack_int <= up_rreq_s;
if (up_rreq_s == 1'b1) begin if (up_rreq_s == 1'b1) begin
case (up_raddr[3:0]) case (up_raddr[3:0])
4'h0: up_rdata <= {20'd0, up_adc_lb_enb, up_adc_pn_sel, 4'h0: up_rdata_int <= { 20'd0, up_adc_lb_enb, up_adc_pn_sel,
up_adc_iqcor_enb, up_adc_dcfilt_enb, up_adc_iqcor_enb, up_adc_dcfilt_enb,
1'd0, up_adc_dfmt_se, up_adc_dfmt_type, up_adc_dfmt_enable, 1'd0, up_adc_dfmt_se, up_adc_dfmt_type, up_adc_dfmt_enable,
2'd0, up_adc_pn_type, up_adc_enable}; 2'd0, up_adc_pn_type, up_adc_enable};
4'h1: up_rdata <= {29'd0, up_adc_pn_err, up_adc_pn_oos, up_adc_or}; 4'h1: up_rdata_int <= { 29'd0, up_adc_pn_err_int, up_adc_pn_oos_int, up_adc_or_int};
4'h4: up_rdata <= {up_adc_dcfilt_offset, up_adc_dcfilt_coeff}; 4'h4: up_rdata_int <= { up_adc_dcfilt_offset, up_adc_dcfilt_coeff};
4'h5: up_rdata <= {up_adc_iqcor_coeff_1, up_adc_iqcor_coeff_2}; 4'h5: up_rdata_int <= { up_adc_iqcor_coeff_1, up_adc_iqcor_coeff_2};
4'h6: up_rdata <= {12'd0, up_adc_pnseq_sel, 12'd0, up_adc_data_sel}; 4'h6: up_rdata_int <= { 12'd0, up_adc_pnseq_sel, 12'd0, up_adc_data_sel};
4'h8: up_rdata <= {6'd0, adc_usr_datatype_be, adc_usr_datatype_signed, 4'h8: up_rdata_int <= { 6'd0, adc_usr_datatype_be, adc_usr_datatype_signed,
adc_usr_datatype_shift, adc_usr_datatype_total_bits, adc_usr_datatype_shift, adc_usr_datatype_total_bits,
adc_usr_datatype_bits}; adc_usr_datatype_bits};
4'h9: up_rdata <= {adc_usr_decimation_m, adc_usr_decimation_n}; 4'h9: up_rdata_int <= { adc_usr_decimation_m, adc_usr_decimation_n};
default: up_rdata <= 0; default: up_rdata_int <= 0;
endcase endcase
end else begin end else begin
up_rdata <= 32'd0; up_rdata_int <= 32'd0;
end end
end end
end end

322
library/common/up_adc_common.v
View File

@ -37,129 +37,80 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module up_adc_common ( module up_adc_common #(
// clock reset
mmcm_rst,
// adc interface
adc_clk,
adc_rst,
adc_r1_mode,
adc_ddr_edgesel,
adc_pin_mode,
adc_status,
adc_sync_status,
adc_status_ovf,
adc_status_unf,
adc_clk_ratio,
adc_start_code,
adc_sync,
// channel interface
up_status_pn_err,
up_status_pn_oos,
up_status_or,
// drp interface
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_locked,
// user channel control
up_usr_chanmax,
adc_usr_chanmax,
up_adc_gpio_in,
up_adc_gpio_out,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters // parameters
localparam PCORE_VERSION = 32'h00090062; parameter ID = 0,
parameter ID = 0; parameter CONFIG = 0,
parameter ADC_COMMON_ID = 6'h00; parameter COMMON_ID = 6'h00,
parameter DRP_DISABLE = 6'h00,
parameter USERPORTS_DISABLE = 0) (
// clock reset // clock reset
output mmcm_rst; output mmcm_rst,
// adc interface // adc interface
input adc_clk; input adc_clk,
output adc_rst; output adc_rst,
output adc_r1_mode; output adc_r1_mode,
output adc_ddr_edgesel; output adc_ddr_edgesel,
output adc_pin_mode; output adc_pin_mode,
input adc_status; input adc_status,
input adc_sync_status; input adc_sync_status,
input adc_status_ovf; input adc_status_ovf,
input adc_status_unf; input adc_status_unf,
input [31:0] adc_clk_ratio; input [31:0] adc_clk_ratio,
output [31:0] adc_start_code; output [31:0] adc_start_code,
output adc_sync; output adc_sync,
// channel interface // channel interface
input up_status_pn_err; input up_status_pn_err,
input up_status_pn_oos; input up_status_pn_oos,
input up_status_or; input up_status_or,
// drp interface // drp interface
output up_drp_sel; output up_drp_sel,
output up_drp_wr; output up_drp_wr,
output [11:0] up_drp_addr; output [11:0] up_drp_addr,
output [31:0] up_drp_wdata; output [31:0] up_drp_wdata,
input [31:0] up_drp_rdata; input [31:0] up_drp_rdata,
input up_drp_ready; input up_drp_ready,
input up_drp_locked; input up_drp_locked,
// user channel control // user channel control
output [ 7:0] up_usr_chanmax; output [ 7:0] up_usr_chanmax,
input [ 7:0] adc_usr_chanmax; input [ 7:0] adc_usr_chanmax,
input [31:0] up_adc_gpio_in; input [31:0] up_adc_gpio_in,
output [31:0] up_adc_gpio_out; output [31:0] up_adc_gpio_out,
// bus interface // bus interface
input up_rstn; input up_rstn,
input up_clk; input up_clk,
input up_wreq; input up_wreq,
input [13:0] up_waddr; input [13:0] up_waddr,
input [31:0] up_wdata; input [31:0] up_wdata,
output up_wack; output up_wack,
input up_rreq; input up_rreq,
input [13:0] up_raddr; input [13:0] up_raddr,
output [31:0] up_rdata; output [31:0] up_rdata,
output up_rack; output up_rack);
// parameters
localparam VERSION = 32'h000a0062;
// internal registers // internal registers
reg up_core_preset = 'd0; reg up_core_preset = 'd0;
reg up_mmcm_preset = 'd0; reg up_mmcm_preset = 'd0;
reg up_wack = 'd0; reg up_wack_int = 'd0;
reg [31:0] up_scratch = 'd0; reg [31:0] up_scratch = 'd0;
reg up_mmcm_resetn = 'd0; reg up_mmcm_resetn = 'd0;
reg up_resetn = 'd0; reg up_resetn = 'd0;
@ -167,20 +118,20 @@ module up_adc_common (
reg up_adc_r1_mode = 'd0; reg up_adc_r1_mode = 'd0;
reg up_adc_ddr_edgesel = 'd0; reg up_adc_ddr_edgesel = 'd0;
reg up_adc_pin_mode = 'd0; reg up_adc_pin_mode = 'd0;
reg up_drp_sel = 'd0; reg up_drp_sel_int = 'd0;
reg up_drp_wr = 'd0; reg up_drp_wr_int = 'd0;
reg up_drp_status = 'd0; reg up_drp_status = 'd0;
reg up_drp_rwn = 'd0; reg up_drp_rwn = 'd0;
reg [11:0] up_drp_addr = 'd0; reg [11:0] up_drp_addr_int = 'd0;
reg [31:0] up_drp_wdata = 'd0; reg [31:0] up_drp_wdata_int = 'd0;
reg [31:0] up_drp_rdata_hold = 'd0; reg [31:0] up_drp_rdata_hold = 'd0;
reg up_status_ovf = 'd0; reg up_status_ovf = 'd0;
reg up_status_unf = 'd0; reg up_status_unf = 'd0;
reg [ 7:0] up_usr_chanmax = 'd0; reg [ 7:0] up_usr_chanmax_int = 'd0;
reg [31:0] up_adc_start_code = 'd0; reg [31:0] up_adc_start_code = 'd0;
reg [31:0] up_adc_gpio_out = 'd0; reg [31:0] up_adc_gpio_out_int = 'd0;
reg up_rack = 'd0; reg up_rack_int = 'd0;
reg [31:0] up_rdata = 'd0; reg [31:0] up_rdata_int = 'd0;
// internal signals // internal signals
@ -195,16 +146,18 @@ module up_adc_common (
// decode block select // decode block select
assign up_wreq_s = (up_waddr[13:8] == ADC_COMMON_ID) ? up_wreq : 1'b0; assign up_wreq_s = (up_waddr[13:8] == COMMON_ID) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == ADC_COMMON_ID) ? up_rreq : 1'b0; assign up_rreq_s = (up_raddr[13:8] == COMMON_ID) ? up_rreq : 1'b0;
// processor write interface // processor write interface
assign up_wack = up_wack_int;
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin if (up_rstn == 0) begin
up_core_preset <= 1'd1; up_core_preset <= 1'd1;
up_mmcm_preset <= 1'd1; up_mmcm_preset <= 1'd1;
up_wack <= 'd0; up_wack_int <= 'd0;
up_scratch <= 'd0; up_scratch <= 'd0;
up_mmcm_resetn <= 'd0; up_mmcm_resetn <= 'd0;
up_resetn <= 'd0; up_resetn <= 'd0;
@ -212,22 +165,10 @@ module up_adc_common (
up_adc_r1_mode <= 'd0; up_adc_r1_mode <= 'd0;
up_adc_ddr_edgesel <= 'd0; up_adc_ddr_edgesel <= 'd0;
up_adc_pin_mode <= 'd0; up_adc_pin_mode <= 'd0;
up_drp_sel <= 'd0;
up_drp_wr <= 'd0;
up_drp_status <= 'd0;
up_drp_rwn <= 'd0;
up_drp_addr <= 'd0;
up_drp_wdata <= 'd0;
up_drp_rdata_hold <= 'd0;
up_status_ovf <= 'd0;
up_status_unf <= 'd0;
up_usr_chanmax <= 'd0;
up_adc_start_code <= 'd0;
up_adc_gpio_out <= 'd0;
end else begin end else begin
up_core_preset <= ~up_resetn; up_core_preset <= ~up_resetn;
up_mmcm_preset <= ~up_mmcm_resetn; up_mmcm_preset <= ~up_mmcm_resetn;
up_wack <= up_wreq_s; up_wack_int <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata; up_scratch <= up_wdata;
end end
@ -247,12 +188,42 @@ module up_adc_common (
up_adc_ddr_edgesel <= up_wdata[1]; up_adc_ddr_edgesel <= up_wdata[1];
up_adc_pin_mode <= up_wdata[0]; up_adc_pin_mode <= up_wdata[0];
end end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin end
up_drp_sel <= 1'b1; end
up_drp_wr <= ~up_wdata[28];
assign up_drp_sel = up_drp_sel_int;
assign up_drp_wr = up_drp_wr_int;
assign up_drp_addr = up_drp_addr_int;
assign up_drp_wdata = up_drp_wdata_int;
generate
if (DRP_DISABLE == 1) begin
always @(posedge up_clk) begin
up_drp_sel_int <= 'd0;
up_drp_wr_int <= 'd0;
up_drp_status <= 'd0;
up_drp_rwn <= 'd0;
up_drp_addr_int <= 'd0;
up_drp_wdata_int <= 'd0;
up_drp_rdata_hold <= 'd0;
end
end else begin end else begin
up_drp_sel <= 1'b0; always @(negedge up_rstn or posedge up_clk) begin
up_drp_wr <= 1'b0; if (up_rstn == 0) begin
up_drp_sel_int <= 'd0;
up_drp_wr_int <= 'd0;
up_drp_status <= 'd0;
up_drp_rwn <= 'd0;
up_drp_addr_int <= 'd0;
up_drp_wdata_int <= 'd0;
up_drp_rdata_hold <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_sel_int <= 1'b1;
up_drp_wr_int <= ~up_wdata[28];
end else begin
up_drp_sel_int <= 1'b0;
up_drp_wr_int <= 1'b0;
end end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_status <= 1'b1; up_drp_status <= 1'b1;
@ -261,14 +232,24 @@ module up_adc_common (
end end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_rwn <= up_wdata[28]; up_drp_rwn <= up_wdata[28];
up_drp_addr <= up_wdata[27:16]; up_drp_addr_int <= up_wdata[27:16];
end end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1e)) begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1e)) begin
up_drp_wdata <= up_wdata; up_drp_wdata_int <= up_wdata;
end end
if (up_drp_ready == 1'b1) begin if (up_drp_ready == 1'b1) begin
up_drp_rdata_hold <= up_drp_rdata; up_drp_rdata_hold <= up_drp_rdata;
end end
end
end
end
endgenerate
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_status_ovf <= 'd0;
up_status_unf <= 'd0;
end else begin
if (up_status_ovf_s == 1'b1) begin if (up_status_ovf_s == 1'b1) begin
up_status_ovf <= 1'b1; up_status_ovf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
@ -279,51 +260,82 @@ module up_adc_common (
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_status_unf <= up_status_unf & ~up_wdata[1]; up_status_unf <= up_status_unf & ~up_wdata[1];
end end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
up_usr_chanmax <= up_wdata[7:0];
end end
end
assign up_usr_chanmax = up_usr_chanmax_int;
generate
if (USERPORTS_DISABLE == 1) begin
always @(posedge up_clk) begin
up_usr_chanmax_int <= 'd0;
end
end else begin
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_usr_chanmax_int <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
up_usr_chanmax_int <= up_wdata[7:0];
end
end
end
end
endgenerate
assign up_adc_gpio_out = up_adc_gpio_out_int;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_adc_start_code <= 'd0;
up_adc_gpio_out_int <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h29)) begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h29)) begin
up_adc_start_code <= up_wdata[31:0]; up_adc_start_code <= up_wdata[31:0];
end end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2f)) begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2f)) begin
up_adc_gpio_out <= up_wdata; up_adc_gpio_out_int <= up_wdata;
end end
end end
end end
// processor read interface // processor read interface
assign up_rack = up_rack_int;
assign up_rdata = up_rdata_int;
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin if (up_rstn == 0) begin
up_rack <= 'd0; up_rack_int <= 'd0;
up_rdata <= 'd0; up_rdata_int <= 'd0;
end else begin end else begin
up_rack <= up_rreq_s; up_rack_int <= up_rreq_s;
if (up_rreq_s == 1'b1) begin if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0]) case (up_raddr[7:0])
8'h00: up_rdata <= PCORE_VERSION; 8'h00: up_rdata_int <= VERSION;
8'h01: up_rdata <= ID; 8'h01: up_rdata_int <= ID;
8'h02: up_rdata <= up_scratch; 8'h02: up_rdata_int <= up_scratch;
8'h10: up_rdata <= {30'd0, up_mmcm_resetn, up_resetn}; 8'h03: up_rdata_int <= CONFIG;
8'h11: up_rdata <= {28'd0, up_adc_sync, up_adc_r1_mode, up_adc_ddr_edgesel, up_adc_pin_mode}; 8'h10: up_rdata_int <= {30'd0, up_mmcm_resetn, up_resetn};
8'h15: up_rdata <= up_adc_clk_count_s; 8'h11: up_rdata_int <= {28'd0, up_adc_sync, up_adc_r1_mode, up_adc_ddr_edgesel, up_adc_pin_mode};
8'h16: up_rdata <= adc_clk_ratio; 8'h15: up_rdata_int <= up_adc_clk_count_s;
8'h17: up_rdata <= {28'd0, up_status_pn_err, up_status_pn_oos, up_status_or, up_status_s}; 8'h16: up_rdata_int <= adc_clk_ratio;
8'h1a: up_rdata <= {31'd0, up_sync_status_s}; 8'h17: up_rdata_int <= {28'd0, up_status_pn_err, up_status_pn_oos, up_status_or, up_status_s};
8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, 16'b0}; 8'h1a: up_rdata_int <= {31'd0, up_sync_status_s};
8'h1d: up_rdata <= {14'd0, up_drp_locked, up_drp_status, 16'b0}; 8'h1c: up_rdata_int <= {3'd0, up_drp_rwn, up_drp_addr_int, 16'b0};
8'h1e: up_rdata <= up_drp_wdata; 8'h1d: up_rdata_int <= {14'd0, up_drp_locked, up_drp_status, 16'b0};
8'h1f: up_rdata <= up_drp_rdata_hold; 8'h1e: up_rdata_int <= up_drp_wdata_int;
8'h22: up_rdata <= {29'd0, up_status_ovf, up_status_unf, 1'b0}; 8'h1f: up_rdata_int <= up_drp_rdata_hold;
8'h23: up_rdata <= 32'd8; 8'h22: up_rdata_int <= {29'd0, up_status_ovf, up_status_unf, 1'b0};
8'h28: up_rdata <= {24'd0, adc_usr_chanmax}; 8'h23: up_rdata_int <= 32'd8;
8'h29: up_rdata <= up_adc_start_code; 8'h28: up_rdata_int <= {24'd0, adc_usr_chanmax};
8'h2e: up_rdata <= up_adc_gpio_in; 8'h29: up_rdata_int <= up_adc_start_code;
8'h2f: up_rdata <= up_adc_gpio_out; 8'h2e: up_rdata_int <= up_adc_gpio_in;
default: up_rdata <= 0; 8'h2f: up_rdata_int <= up_adc_gpio_out_int;
default: up_rdata_int <= 0;
endcase endcase
end else begin end else begin
up_rdata <= 32'd0; up_rdata_int <= 32'd0;
end end
end end
end end