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axi_logic_analyzer: Fix delayed trigger assertion condition

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Adrian Costina 2017-06-19 10:58:22 +03:00
parent d840baee28
commit 871855c9ec
1 changed files with 1 additions and 1 deletions
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library/axi_logic_analyzer/axi_logic_analyzer.v
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@ -140,7 +140,7 @@ module axi_logic_analyzer (
assign up_rstn = s_axi_aresetn;
assign trigger_out = trigger_delay == 32'h0 ? trigger_out_s : trigger_out_delayed;
assign trigger_out_delayed = trigger_delay == 32'h0 ? 1: 0;
assign trigger_out_delayed = delay_counter == 32'h0 ? 1 : 0;
generate
for (i = 0 ; i < 16; i = i + 1) begin