From 860a7caa56f11a6d8dd9a9d45f12b0a3a615c87d Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Fri, 31 Oct 2014 12:04:34 +0200 Subject: [PATCH] prcfg: dac and adc to dma interface width is 64 --- projects/fmcomms2_pr/common/prcfg_setup.tcl | 10 ++-- .../fmcomms2_pr/common/prcfg_system_top.v | 48 ++++--------------- projects/fmcomms2_pr/mitx045/system_top.v | 16 +++---- 3 files changed, 23 insertions(+), 51 deletions(-) diff --git a/projects/fmcomms2_pr/common/prcfg_setup.tcl b/projects/fmcomms2_pr/common/prcfg_setup.tcl index 31cb39fb3..531c83405 100644 --- a/projects/fmcomms2_pr/common/prcfg_setup.tcl +++ b/projects/fmcomms2_pr/common/prcfg_setup.tcl @@ -1,4 +1,4 @@ -set data_width 127 +set data_width 64 # # Port definitions @@ -81,28 +81,28 @@ set ila_adc_core [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_adc_co set_property -dict [list CONFIG.Component_Name {"pr2adc_core_ila"}] $ila_adc_core set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_adc_core set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc_core -set_property -dict [list CONFIG.C_PROBE1_WIDTH {128}] $ila_adc_core +set_property -dict [list CONFIG.C_PROBE1_WIDTH {64}] $ila_adc_core set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc_core set ila_dac_core [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_dac_core] set_property -dict [list CONFIG.Component_Name {"pr2dac_core_ila"}] $ila_dac_core set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_dac_core set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_dac_core -set_property -dict [list CONFIG.C_PROBE1_WIDTH {128}] $ila_dac_core +set_property -dict [list CONFIG.C_PROBE1_WIDTH {64}] $ila_dac_core set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_dac_core set ila_adc_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_adc_dma] set_property -dict [list CONFIG.Component_Name {"pr2adc_dma_ila"}] $ila_adc_dma set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_adc_dma set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc_dma -set_property -dict [list CONFIG.C_PROBE1_WIDTH {128}] $ila_adc_dma +set_property -dict [list CONFIG.C_PROBE1_WIDTH {64}] $ila_adc_dma set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc_dma set ila_dac_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_dac_dma] set_property -dict [list CONFIG.Component_Name {"pr2dac_dma_ila"}] $ila_dac_dma set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_dac_dma set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_dac_dma -set_property -dict [list CONFIG.C_PROBE1_WIDTH {128}] $ila_dac_dma +set_property -dict [list CONFIG.C_PROBE1_WIDTH {64}] $ila_dac_dma set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_dac_dma connect_bd_net [get_bd_pins ila_adc_core/clk] [get_bd_ports clk] diff --git a/projects/fmcomms2_pr/common/prcfg_system_top.v b/projects/fmcomms2_pr/common/prcfg_system_top.v index 676fa83f4..a21d03dfc 100644 --- a/projects/fmcomms2_pr/common/prcfg_system_top.v +++ b/projects/fmcomms2_pr/common/prcfg_system_top.v @@ -81,22 +81,22 @@ module prcfg_system_top ( output dma_dac_en; input dma_dac_dunf; - input [127:0] dma_dac_ddata; + input [63:0] dma_dac_ddata; input dma_dac_dvalid; input core_dac_en; output core_dac_dunf; - output [127:0] core_dac_ddata; + output [63:0] core_dac_ddata; output core_dac_dvalid; input core_adc_dwr; input core_adc_dsync; - input [127:0] core_adc_ddata; + input [63:0] core_adc_ddata; output core_adc_ovf; output dma_adc_dwr; output dma_adc_dsync; - output [127:0] dma_adc_ddata; + output [63:0] dma_adc_ddata; input dma_adc_ovf; @@ -113,7 +113,7 @@ module prcfg_system_top ( .NUM_CHANNEL(NUM_CHANNEL), .ADC_EN(ENABLE), .DAC_EN(ENABLE) - )i_prcfg_top_smp0 ( + )i_prcfg_top ( .clk(clk), .adc_gpio_input(adc_gpio_input), .adc_gpio_output(adc_gpio_output), @@ -121,47 +121,19 @@ module prcfg_system_top ( .dac_gpio_output(dac_gpio_output), .dma_dac_en(dma_dac_en), .dma_dac_dunf(dma_dac_dunf), - .dma_dac_ddata(dma_dac_ddata[63:0]), + .dma_dac_ddata(dma_dac_ddata), .dma_dac_dvalid(dma_dac_dvalid), .core_dac_en(core_dac_en), .core_dac_dunf(core_dac_dunf), - .core_dac_ddata(core_dac_ddata[63:0]), + .core_dac_ddata(core_dac_ddata), .core_dac_dvalid(core_dac_dvalid), .core_adc_dwr(core_adc_dwr), .core_adc_dsync(core_adc_dsync), - .core_adc_ddata(core_adc_ddata[63:0]), + .core_adc_ddata(core_adc_ddata), .core_adc_ovf(core_adc_ovf), .dma_adc_dwr(dma_adc_dwr), .dma_adc_dsync(dma_adc_dsync), - .dma_adc_ddata(dma_adc_ddata[63:0]), - .dma_adc_ovf(dma_adc_ovf) -); + .dma_adc_ddata(dma_adc_ddata), + .dma_adc_ovf(dma_adc_ovf)); - prcfg_top #( - .NUM_CHANNEL(NUM_CHANNEL), - .ADC_EN(ENABLE), - .DAC_EN(ENABLE) - )i_prcfg_top_smp1 ( - .clk(clk), - .adc_gpio_input(adc_gpio_input), - .adc_gpio_output(), - .dac_gpio_input(dac_gpio_input), - .dac_gpio_output(), - .dma_dac_en(), - .dma_dac_dunf(dma_dac_dunf), - .dma_dac_ddata(dma_dac_ddata[127:64]), - .dma_dac_dvalid(dma_dac_dvalid), - .core_dac_en(core_dac_en), - .core_dac_dunf(), - .core_dac_ddata(core_dac_ddata[127:64]), - .core_dac_dvalid(), - .core_adc_dwr(core_adc_dwr), - .core_adc_dsync(core_adc_dsync), - .core_adc_ddata(core_adc_ddata[127:64]), - .core_adc_ovf(), - .dma_adc_dwr(), - .dma_adc_dsync(), - .dma_adc_ddata(dma_adc_ddata[127:64]), - .dma_adc_ovf(dma_adc_ovf) -); endmodule diff --git a/projects/fmcomms2_pr/mitx045/system_top.v b/projects/fmcomms2_pr/mitx045/system_top.v index f41c58489..5f14a7596 100644 --- a/projects/fmcomms2_pr/mitx045/system_top.v +++ b/projects/fmcomms2_pr/mitx045/system_top.v @@ -187,8 +187,8 @@ module system_top ( wire clk; wire dma_dac_dunf; wire core_dac_dunf; - wire [127:0] dma_dac_ddata; - wire [127:0] core_dac_ddata; + wire [63:0] dma_dac_ddata; + wire [63:0] core_dac_ddata; wire dma_dac_en; wire core_dac_en; wire dma_dac_dvalid; @@ -196,8 +196,8 @@ module system_top ( wire dma_adc_ovf; wire core_adc_ovf; - wire [127:0] dma_adc_ddata; - wire [127:0] core_adc_ddata; + wire [63:0] dma_adc_ddata; + wire [63:0] core_adc_ddata; wire dma_adc_dwr; wire core_adc_dwr; wire dma_adc_dsync; @@ -348,19 +348,19 @@ endmodule output [31:0] dac_gpio_output, output dma_dac_en, input dma_dac_dunf, - input [127:0] dma_dac_ddata, + input [63:0] dma_dac_ddata, input dma_dac_dvalid, input core_dac_en, output core_dac_dunf, - output [127:0] core_dac_ddata, + output [63:0] core_dac_ddata, output core_dac_dvalid, input core_adc_dwr, input core_adc_dsync, - input [127:0] core_adc_ddata, + input [63:0] core_adc_ddata, output core_adc_ovf, output dma_adc_dwr, output dma_adc_dsync, - output [127:0] dma_adc_ddata, + output [63:0] dma_adc_ddata, input dma_adc_ovf); endmodule