zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fmcjesdadc1/a5*- updates

main
Rejeesh Kutty 2016-11-10 16:57:06 -05:00
parent 959055bd54
commit 85eac8c811
3 changed files with 152 additions and 162 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
projects/fmcjesdadc1/a5gt/system_constr.sdc
View File

@ -1,17 +1,27 @@
create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
create_clock -period "4.000 ns" -name ref_clk_250mhz [get_ports {ref_clk}]
create_clock -period "8.000 ns" -name eth_rx_clk_125mhz [get_ports {eth_rx_clk}]
create_clock -period "10.000 ns" -name sys_clk [get_ports {sys_clk}]
create_clock -period "4.000 ns" -name ref_clk [get_ports {ref_clk}]
create_clock -period "8.000 ns" -name eth_rx_clk [get_ports {eth_rx_clk}]
derive_pll_clocks
derive_clock_uncertainty
set_clock_groups -exclusive \
-group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}]
-group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}]
set_false_path -to [get_registers {rx_sysref_m1}]
set_false_path -from [get_clocks {sys_clk}] -through [get_nets *altera_jesd204_rx_ctl_inst*]\
-to [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]
set_false_path -from [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]\
-through [get_nets *altera_jesd204_rx_ctl_inst*] -to [get_clocks {sys_clk}]
set_false_path -from [get_clocks {sys_clk}] -through [get_nets *altera_jesd204_rx_csr_inst*]\
-to [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]
set_false_path -from [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]\
-through [get_nets *altera_jesd204_rx_csr_inst*] -to [get_clocks {sys_clk}]
set_clock_groups -asynchronous \
-group {ref_clk_250mhz} \
-group [get_clocks {i_system_bd|fmcjesdadc1|xcvr_rx_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}]

282
projects/fmcjesdadc1/a5gt/system_top.v
View File

@ -41,136 +41,85 @@ module system_top (
// clock and resets
sys_clk,
sys_resetn,
input sys_clk,
input sys_resetn,
// ddr3
ddr3_clk_p,
ddr3_clk_n,
ddr3_a,
ddr3_ba,
ddr3_cke,
ddr3_cs_n,
ddr3_odt,
ddr3_reset_n,
ddr3_we_n,
ddr3_ras_n,
ddr3_cas_n,
ddr3_dqs_p,
ddr3_dqs_n,
ddr3_dq,
ddr3_dm,
ddr3_rzq,
output ddr3_clk_p,
output ddr3_clk_n,
output [ 13:0] ddr3_a,
output [ 2:0] ddr3_ba,
output ddr3_cke,
output ddr3_cs_n,
output ddr3_odt,
output ddr3_reset_n,
output ddr3_we_n,
output ddr3_ras_n,
output ddr3_cas_n,
inout [ 7:0] ddr3_dqs_p,
inout [ 7:0] ddr3_dqs_n,
inout [ 63:0] ddr3_dq,
output [ 7:0] ddr3_dm,
input ddr3_rzq,
// ethernet
eth_rx_clk,
eth_rx_data,
eth_rx_cntrl,
eth_tx_clk_out,
eth_tx_data,
eth_tx_cntrl,
eth_mdc,
eth_mdio_i,
eth_mdio_o,
eth_mdio_t,
eth_phy_resetn,
input eth_rx_clk,
input [ 3:0] eth_rx_data,
input eth_rx_cntrl,
output eth_tx_clk_out,
output [ 3:0] eth_tx_data,
output eth_tx_cntrl,
output eth_mdc,
input eth_mdio_i,
output eth_mdio_o,
output eth_mdio_t,
output eth_phy_resetn,
// board gpio
gpio_bd,
output [ 15:0] gpio_bd_o,
input [ 10:0] gpio_bd_i,
// lane interface
ref_clk,
rx_data,
rx_sync,
rx_sysref,
input ref_clk,
input [ 3:0] rx_data,
output rx_sync,
output rx_sysref,
// spi
spi_csn,
spi_clk,
spi_sdio);
// clock and resets
input sys_clk;
input sys_resetn;
// ddr3
output ddr3_clk_p;
output ddr3_clk_n;
output [ 13:0] ddr3_a;
output [ 2:0] ddr3_ba;
output ddr3_cke;
output ddr3_cs_n;
output ddr3_odt;
output ddr3_reset_n;
output ddr3_we_n;
output ddr3_ras_n;
output ddr3_cas_n;
inout [ 7:0] ddr3_dqs_p;
inout [ 7:0] ddr3_dqs_n;
inout [ 63:0] ddr3_dq;
output [ 7:0] ddr3_dm;
input ddr3_rzq;
// ethernet
input eth_rx_clk;
input [ 3:0] eth_rx_data;
input eth_rx_cntrl;
output eth_tx_clk_out;
output [ 3:0] eth_tx_data;
output eth_tx_cntrl;
output eth_mdc;
input eth_mdio_i;
output eth_mdio_o;
output eth_mdio_t;
output eth_phy_resetn;
// board gpio
output [ 26:0] gpio_bd;
// lane interface
input ref_clk;
input [ 3:0] rx_data;
output rx_sync;
output rx_sysref;
// spi
output spi_csn;
output spi_clk;
inout spi_sdio;
output spi_csn,
output spi_clk,
inout spi_sdio);
// internal registers
reg [ 3:0] phy_rst_cnt = 0;
reg phy_rst_reg = 0;
reg rx_sysref_m1 = 'd0;
reg rx_sysref_m2 = 'd0;
reg rx_sysref_int = 'd0;
// internal clocks and resets
// internal signals
wire sys_125m_clk;
wire sys_25m_clk;
wire sys_2m5_clk;
wire eth_tx_clk;
wire rx_clk;
// internal signals
wire sys_pll_locked;
wire eth_tx_clk;
wire eth_tx_mode_1g;
wire eth_tx_mode_10m_100m_n;
wire rx_clk;
wire [ 3:0] rx_ip_sof;
wire [127:0] rx_ip_data;
wire spi_mosi;
wire spi_miso;
wire [ 63:0] gpio_i;
wire [ 63:0] gpio_o;
wire [ 7:0] spi_csn_s;
// ethernet transmit clock
@ -186,19 +135,34 @@ module system_top (
end
end
// gpio
assign gpio_i[63:11] = gpio_o[63:11];
assign gpio_i[10: 0] = gpio_bd_i;
assign gpio_bd_o = gpio_o[26:11];
// sysref
assign rx_sysref = rx_sysref_int;
always @(posedge rx_clk) begin
rx_sysref_m1 <= gpio_o[32];
rx_sysref_m2 <= rx_sysref_m1;
rx_sysref_int <= rx_sysref_m1 & ~rx_sysref_m2;
end
// instantiations
assign spi_csn = spi_csn_s[0];
fmcjesdadc1_spi i_fmcjesdadc1_spi (
.spi_csn (spi_csn),
.spi_csn (spi_csn_s[0]),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi),
.spi_miso (spi_miso),
.spi_sdio (spi_sdio));
ad_iobuf #(.DATA_WIDTH(27)) i_iobuf_bd (
.dio_t ({11'h7ff, 16'h0}),
.dio_i (gpio_o[26:0]),
.dio_o (gpio_i[26:0]),
.dio_p (gpio_bd));
altddio_out #(.width(1)) i_eth_tx_clk_out (
.aset (1'b0),
.sset (1'b0),
@ -213,54 +177,70 @@ module system_top (
.dataout (eth_tx_clk_out));
system_bd i_system_bd (
.a5gt_base_sys_ddr3_oct_rzqin (ddr3_rzq),
.a5gt_base_sys_ddr3_phy_mem_a (ddr3_a),
.a5gt_base_sys_ddr3_phy_mem_ba (ddr3_ba),
.a5gt_base_sys_ddr3_phy_mem_ck (ddr3_clk_p),
.a5gt_base_sys_ddr3_phy_mem_ck_n (ddr3_clk_n),
.a5gt_base_sys_ddr3_phy_mem_cke (ddr3_cke),
.a5gt_base_sys_ddr3_phy_mem_cs_n (ddr3_cs_n),
.a5gt_base_sys_ddr3_phy_mem_dm (ddr3_dm),
.a5gt_base_sys_ddr3_phy_mem_ras_n (ddr3_ras_n),
.a5gt_base_sys_ddr3_phy_mem_cas_n (ddr3_cas_n),
.a5gt_base_sys_ddr3_phy_mem_we_n (ddr3_we_n),
.a5gt_base_sys_ddr3_phy_mem_reset_n (ddr3_reset_n),
.a5gt_base_sys_ddr3_phy_mem_dq (ddr3_dq),
.a5gt_base_sys_ddr3_phy_mem_dqs (ddr3_dqs_p),
.a5gt_base_sys_ddr3_phy_mem_dqs_n (ddr3_dqs_n),
.a5gt_base_sys_ddr3_phy_mem_odt (ddr3_odt),
.a5gt_base_sys_125m_clk_clk (sys_125m_clk),
.a5gt_base_sys_25m_clk_clk (sys_25m_clk),
.a5gt_base_sys_2m5_clk_clk (sys_2m5_clk),
.a5gt_base_sys_ethernet_mdio_mdc (eth_mdc),
.a5gt_base_sys_ethernet_mdio_mdio_in (eth_mdio_i),
.a5gt_base_sys_ethernet_mdio_mdio_out (eth_mdio_o),
.a5gt_base_sys_ethernet_mdio_mdio_oen (eth_mdio_t),
.a5gt_base_sys_ethernet_rgmii_rgmii_in (eth_rx_data),
.a5gt_base_sys_ethernet_rgmii_rgmii_out (eth_tx_data),
.a5gt_base_sys_ethernet_rgmii_rx_control (eth_rx_cntrl),
.a5gt_base_sys_ethernet_rgmii_tx_control (eth_tx_cntrl),
.a5gt_base_sys_ethernet_rx_clk_clk (eth_rx_clk),
.a5gt_base_sys_ethernet_status_set_10 (),
.a5gt_base_sys_ethernet_status_set_1000 (),
.a5gt_base_sys_ethernet_status_eth_mode (eth_tx_mode_1g),
.a5gt_base_sys_ethernet_status_ena_10 (eth_tx_mode_10m_100m_n),
.a5gt_base_sys_ethernet_tx_clk_clk (eth_tx_clk),
.a5gt_base_sys_gpio_in_port (gpio_i[63:32]),
.a5gt_base_sys_gpio_out_port (gpio_o[63:32]),
.a5gt_base_sys_gpio_bd_in_port (gpio_i[31:0]),
.a5gt_base_sys_gpio_bd_out_port (gpio_o[31:0]),
.a5gt_base_sys_pll_locked_export (sys_pll_locked),
.a5gt_base_sys_spi_MISO (spi_miso),
.a5gt_base_sys_spi_MOSI (spi_mosi),
.a5gt_base_sys_spi_SCLK (spi_clk),
.a5gt_base_sys_spi_SS_n (spi_csn),
.rx_data_rx_serial_data (rx_data),
.rx_core_clk_clk (rx_clk),
.rx_data_0_rx_serial_data (rx_data[0]),
.rx_data_1_rx_serial_data (rx_data[1]),
.rx_data_2_rx_serial_data (rx_data[2]),
.rx_data_3_rx_serial_data (rx_data[3]),
.rx_ip_data_data (rx_ip_data),
.rx_ip_data_valid (),
.rx_ip_data_ready (1'b1),
.rx_ip_data_0_data (rx_ip_data[63:0]),
.rx_ip_data_0_valid (1'b1),
.rx_ip_data_0_ready (),
.rx_ip_data_1_data (rx_ip_data[127:64]),
.rx_ip_data_1_valid (1'b1),
.rx_ip_data_1_ready (),
.rx_ip_sof_export (rx_ip_sof),
.rx_ip_sof_0_export (rx_ip_sof),
.rx_ip_sof_1_export (rx_ip_sof),
.rx_ref_clk_clk (ref_clk),
.rx_sync_rx_sync (rx_sync),
.rx_sysref_rx_ext_sysref_out (rx_sysref),
.rx_sync_export (rx_sync),
.rx_sysref_export (rx_sysref_int),
.sys_125m_clk_clk (sys_125m_clk),
.sys_25m_clk_clk (sys_25m_clk),
.sys_2m5_clk_clk (sys_2m5_clk),
.sys_clk_clk (sys_clk),
.sys_reset_reset_n (sys_resetn));
.sys_ddr3_cntrl_mem_mem_a (ddr3_a),
.sys_ddr3_cntrl_mem_mem_ba (ddr3_ba),
.sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
.sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
.sys_ddr3_cntrl_mem_mem_cke (ddr3_cke),
.sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n),
.sys_ddr3_cntrl_mem_mem_dm (ddr3_dm),
.sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n),
.sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n),
.sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n),
.sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n),
.sys_ddr3_cntrl_mem_mem_dq (ddr3_dq),
.sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p),
.sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n),
.sys_ddr3_cntrl_mem_mem_odt (ddr3_odt),
.sys_ddr3_cntrl_oct_rzqin (ddr3_rzq),
.sys_ethernet_mdio_mdc (eth_mdc),
.sys_ethernet_mdio_mdio_in (eth_mdio_i),
.sys_ethernet_mdio_mdio_out (eth_mdio_o),
.sys_ethernet_mdio_mdio_oen (eth_mdio_t),
.sys_ethernet_rgmii_rgmii_in (eth_rx_data),
.sys_ethernet_rgmii_rgmii_out (eth_tx_data),
.sys_ethernet_rgmii_rx_control (eth_rx_cntrl),
.sys_ethernet_rgmii_tx_control (eth_tx_cntrl),
.sys_ethernet_rx_clk_clk (eth_rx_clk),
.sys_ethernet_status_set_10 (),
.sys_ethernet_status_set_1000 (),
.sys_ethernet_status_eth_mode (eth_tx_mode_1g),
.sys_ethernet_status_ena_10 (eth_tx_mode_10m_100m_n),
.sys_ethernet_tx_clk_clk (eth_tx_clk),
.sys_gpio_bd_in_port (gpio_i[31:0]),
.sys_gpio_bd_out_port (gpio_o[31:0]),
.sys_gpio_in_export (gpio_i[63:32]),
.sys_gpio_out_export (gpio_o[63:32]),
.sys_pll_locked_export (sys_pll_locked),
.sys_rst_reset_n (sys_resetn),
.sys_spi_MISO (spi_miso),
.sys_spi_MOSI (spi_mosi),
.sys_spi_SCLK (spi_clk),
.sys_spi_SS_n (spi_csn_s));
endmodule

2
projects/fmcjesdadc1/a5soc/system_top.v
View File

@ -159,7 +159,7 @@ module system_top (
assign rx_sysref = rx_sysref_int;
always @(posedge rx_clk) begin
rx_sysref_m1 <= gpio_o[12];
rx_sysref_m1 <= gpio_o[32];
rx_sysref_m2 <= rx_sysref_m1;
rx_sysref_int <= rx_sysref_m1 & ~rx_sysref_m2;
end