adv7511:vc707: Delete deprecated project
Istvan Csomortani
István Csomortáni
parent
a277d55c35
commit
85913c1b00
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@ -1,19 +0,0 @@
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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PROJECT_NAME := adv7511_vc707
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M_DEPS += ../../common/vc707/vc707_system_mig.prj
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M_DEPS += ../../common/vc707/vc707_system_constr.xdc
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M_DEPS += ../../common/vc707/vc707_system_bd.tcl
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M_DEPS += ../../adv7511/vc707/system_constr.xdc
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M_DEPS += ../../adv7511/common/adv7511_bd.tcl
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M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
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LIB_DEPS += axi_clkgen
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LIB_DEPS += axi_hdmi_tx
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LIB_DEPS += axi_spdif_tx
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include ../../scripts/project-xilinx.mk
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@ -1,4 +0,0 @@
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source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
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source $ad_hdl_dir/projects/adv7511/common/adv7511_bd.tcl
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@ -1,54 +0,0 @@
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# hdmi
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set_property -dict {PACKAGE_PIN AU23 IOSTANDARD LVCMOS18} [get_ports hdmi_out_clk]
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set_property -dict {PACKAGE_PIN AU22 IOSTANDARD LVCMOS18} [get_ports hdmi_hsync]
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set_property -dict {PACKAGE_PIN AT22 IOSTANDARD LVCMOS18} [get_ports hdmi_vsync]
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set_property -dict {PACKAGE_PIN AP21 IOSTANDARD LVCMOS18} [get_ports hdmi_data_e]
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set_property -dict {PACKAGE_PIN AM22 IOSTANDARD LVCMOS18} [get_ports hdmi_data[0]]
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set_property -dict {PACKAGE_PIN AL22 IOSTANDARD LVCMOS18} [get_ports hdmi_data[1]]
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set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVCMOS18} [get_ports hdmi_data[2]]
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set_property -dict {PACKAGE_PIN AJ21 IOSTANDARD LVCMOS18} [get_ports hdmi_data[3]]
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set_property -dict {PACKAGE_PIN AM21 IOSTANDARD LVCMOS18} [get_ports hdmi_data[4]]
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set_property -dict {PACKAGE_PIN AL21 IOSTANDARD LVCMOS18} [get_ports hdmi_data[5]]
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set_property -dict {PACKAGE_PIN AK22 IOSTANDARD LVCMOS18} [get_ports hdmi_data[6]]
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set_property -dict {PACKAGE_PIN AJ22 IOSTANDARD LVCMOS18} [get_ports hdmi_data[7]]
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set_property -dict {PACKAGE_PIN AL20 IOSTANDARD LVCMOS18} [get_ports hdmi_data[8]]
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set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVCMOS18} [get_ports hdmi_data[9]]
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set_property -dict {PACKAGE_PIN AK23 IOSTANDARD LVCMOS18} [get_ports hdmi_data[10]]
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set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS18} [get_ports hdmi_data[11]]
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set_property -dict {PACKAGE_PIN AN21 IOSTANDARD LVCMOS18} [get_ports hdmi_data[12]]
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set_property -dict {PACKAGE_PIN AP22 IOSTANDARD LVCMOS18} [get_ports hdmi_data[13]]
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set_property -dict {PACKAGE_PIN AP23 IOSTANDARD LVCMOS18} [get_ports hdmi_data[14]]
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set_property -dict {PACKAGE_PIN AN23 IOSTANDARD LVCMOS18} [get_ports hdmi_data[15]]
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set_property -dict {PACKAGE_PIN AM23 IOSTANDARD LVCMOS18} [get_ports hdmi_data[16]]
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set_property -dict {PACKAGE_PIN AN24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[17]]
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set_property -dict {PACKAGE_PIN AY24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[18]]
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set_property -dict {PACKAGE_PIN BB22 IOSTANDARD LVCMOS18} [get_ports hdmi_data[19]]
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set_property -dict {PACKAGE_PIN BA22 IOSTANDARD LVCMOS18} [get_ports hdmi_data[20]]
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set_property -dict {PACKAGE_PIN BA25 IOSTANDARD LVCMOS18} [get_ports hdmi_data[21]]
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set_property -dict {PACKAGE_PIN AY25 IOSTANDARD LVCMOS18} [get_ports hdmi_data[22]]
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set_property -dict {PACKAGE_PIN AY22 IOSTANDARD LVCMOS18} [get_ports hdmi_data[23]]
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set_property -dict {PACKAGE_PIN AY23 IOSTANDARD LVCMOS18} [get_ports hdmi_data[24]]
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set_property -dict {PACKAGE_PIN AV24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[25]]
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set_property -dict {PACKAGE_PIN AU24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[26]]
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set_property -dict {PACKAGE_PIN AW21 IOSTANDARD LVCMOS18} [get_ports hdmi_data[27]]
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set_property -dict {PACKAGE_PIN AV21 IOSTANDARD LVCMOS18} [get_ports hdmi_data[28]]
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set_property -dict {PACKAGE_PIN AT24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[29]]
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set_property -dict {PACKAGE_PIN AR24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[30]]
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set_property -dict {PACKAGE_PIN AU21 IOSTANDARD LVCMOS18} [get_ports hdmi_data[31]]
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set_property -dict {PACKAGE_PIN AT21 IOSTANDARD LVCMOS18} [get_ports hdmi_data[32]]
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set_property -dict {PACKAGE_PIN AW22 IOSTANDARD LVCMOS18} [get_ports hdmi_data[33]]
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set_property -dict {PACKAGE_PIN AW23 IOSTANDARD LVCMOS18} [get_ports hdmi_data[34]]
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set_property -dict {PACKAGE_PIN AV23 IOSTANDARD LVCMOS18} [get_ports hdmi_data[35]]
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# spdif
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set_property -dict {PACKAGE_PIN AR23 IOSTANDARD LVCMOS18} [get_ports spdif]
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# spi -- because the interface is not used, the leaf registers of the output lines
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# should be set to IOB FALSE to prevent a CRITICAL WARNING
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set_property IOB FALSE [get_cells i_system_wrapper/system_i/axi_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO0_I_REG]
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set_property IOB FALSE [get_cells i_system_wrapper/system_i/axi_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG]
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@ -1,14 +0,0 @@
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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adi_project_xilinx adv7511_vc707
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adi_project_files adv7511_vc707 [list \
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"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
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"system_top.v" \
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"$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" \
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"$ad_hdl_dir/projects/adv7511/vc707/system_constr.xdc"]
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adi_project_run adv7511_vc707
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@ -1,178 +0,0 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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input sys_rst,
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input sys_clk_p,
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input sys_clk_n,
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input uart_sin,
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output uart_sout,
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output [13:0] ddr3_addr,
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output [ 2:0] ddr3_ba,
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output ddr3_cas_n,
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output [ 0:0] ddr3_ck_n,
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output [ 0:0] ddr3_ck_p,
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output [ 0:0] ddr3_cke,
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output [ 0:0] ddr3_cs_n,
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output [ 7:0] ddr3_dm,
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inout [63:0] ddr3_dq,
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inout [ 7:0] ddr3_dqs_n,
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inout [ 7:0] ddr3_dqs_p,
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output [ 0:0] ddr3_odt,
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output ddr3_ras_n,
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output ddr3_reset_n,
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output ddr3_we_n,
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input sgmii_rxp,
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input sgmii_rxn,
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output sgmii_txp,
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output sgmii_txn,
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output phy_rstn,
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input mgt_clk_p,
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input mgt_clk_n,
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output mdio_mdc,
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inout mdio_mdio,
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output fan_pwm,
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output [26:1] linear_flash_addr,
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output linear_flash_adv_ldn,
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output linear_flash_ce_n,
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output linear_flash_oen,
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output linear_flash_wen,
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inout [15:0] linear_flash_dq_io,
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inout [ 6:0] gpio_lcd,
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inout [20:0] gpio_bd,
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output iic_rstn,
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inout iic_scl,
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inout iic_sda,
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output hdmi_out_clk,
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output hdmi_hsync,
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output hdmi_vsync,
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output hdmi_data_e,
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output [35:0] hdmi_data,
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output spdif);
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// internal signals
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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// default logic
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assign fan_pwm = 1'b1;
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assign iic_rstn = 1'b1;
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ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_sw_led (
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.dio_t (gpio_t[20:0]),
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.dio_i (gpio_o[20:0]),
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.dio_o (gpio_i[20:0]),
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.dio_p (gpio_bd));
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// instantiations
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system_wrapper i_system_wrapper (
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.ddr3_addr (ddr3_addr),
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.ddr3_ba (ddr3_ba),
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.ddr3_cas_n (ddr3_cas_n),
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.ddr3_ck_n (ddr3_ck_n),
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.ddr3_ck_p (ddr3_ck_p),
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.ddr3_cke (ddr3_cke),
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.ddr3_cs_n (ddr3_cs_n),
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.ddr3_dm (ddr3_dm),
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.ddr3_dq (ddr3_dq),
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.ddr3_dqs_n (ddr3_dqs_n),
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.ddr3_dqs_p (ddr3_dqs_p),
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.ddr3_odt (ddr3_odt),
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.ddr3_ras_n (ddr3_ras_n),
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.ddr3_reset_n (ddr3_reset_n),
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.ddr3_we_n (ddr3_we_n),
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.linear_flash_addr (linear_flash_addr),
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.linear_flash_adv_ldn (linear_flash_adv_ldn),
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.linear_flash_ce_n (linear_flash_ce_n),
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.linear_flash_oen (linear_flash_oen),
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.linear_flash_wen (linear_flash_wen),
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.linear_flash_dq_io(linear_flash_dq_io),
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.gpio_lcd_tri_io (gpio_lcd),
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.gpio0_o (gpio_o[31:0]),
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.gpio0_t (gpio_t[31:0]),
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.gpio0_i (gpio_i[31:0]),
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.gpio1_o (gpio_o[63:32]),
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.gpio1_t (gpio_t[63:32]),
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.gpio1_i (gpio_i[63:32]),
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.hdmi_36_data (hdmi_data),
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.hdmi_36_data_e (hdmi_data_e),
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.hdmi_36_hsync (hdmi_hsync),
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.hdmi_out_clk (hdmi_out_clk),
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.hdmi_36_vsync (hdmi_vsync),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.mb_intr_06 (1'b0),
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.mb_intr_12 (1'b0),
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.mb_intr_13 (1'b0),
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.mb_intr_14 (1'b0),
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.mb_intr_15 (1'b0),
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.mdio_mdc (mdio_mdc),
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.mdio_mdio_io (mdio_mdio),
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.mgt_clk_clk_n (mgt_clk_n),
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.mgt_clk_clk_p (mgt_clk_p),
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.phy_rstn (phy_rstn),
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.phy_sd (1'b1),
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.sgmii_rxn (sgmii_rxn),
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.sgmii_rxp (sgmii_rxp),
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.sgmii_txn (sgmii_txn),
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.sgmii_txp (sgmii_txp),
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.spdif (spdif),
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.sys_clk_n (sys_clk_n),
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.sys_clk_p (sys_clk_p),
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.sys_rst (sys_rst),
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.uart_sin (uart_sin),
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.uart_sout (uart_sout));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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