ad9671- xcvr interface changes
Rejeesh Kutty
parent
c114888956
commit
854cd44026
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@ -34,8 +34,6 @@
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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@ -45,8 +43,10 @@ module axi_ad9671 (
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// rx_clk is (line-rate/40)
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rx_clk,
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rx_data,
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rx_sof,
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rx_valid,
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rx_data,
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rx_ready,
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// dma interface
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@ -88,14 +88,15 @@ module axi_ad9671 (
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parameter ID = 0;
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parameter DEVICE_TYPE = 0;
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parameter QUAD_OR_DUAL_N = 1;
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parameter IO_DELAY_GROUP = "adc_if_delay_group";
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// jesd interface
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// rx_clk is the jesd clock (ref_clk/2)
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input rx_clk;
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input [(64*QUAD_OR_DUAL_N)+63:0] rx_data;
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input rx_sof;
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input [ 3:0] rx_sof;
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input rx_valid;
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input [(64*QUAD_OR_DUAL_N)+63:0] rx_data;
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output rx_ready;
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// dma interface
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@ -172,6 +173,7 @@ module axi_ad9671 (
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// signal name changes
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assign rx_ready = 1'b1;
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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@ -201,9 +203,10 @@ module axi_ad9671 (
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// main (device interface)
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axi_ad9671_if #(
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.QUAD_OR_DUAL_N(QUAD_OR_DUAL_N),
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.ID(ID)
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) i_if (
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.QUAD_OR_DUAL_N (QUAD_OR_DUAL_N),
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.ID (ID),
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.DEVICE_TYPE (DEVICE_TYPE))
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i_if (
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.rx_clk (rx_clk),
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.rx_data (rx_data),
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.rx_sof (rx_sof),
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@ -232,8 +235,8 @@ module axi_ad9671 (
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.adc_sync_out (adc_sync_out),
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.adc_sync_status (adc_sync_status_s),
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.adc_status (adc_status_s),
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.adc_raddr_in(adc_raddr_in),
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.adc_raddr_out(adc_raddr_out));
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.adc_raddr_in (adc_raddr_in),
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.adc_raddr_out (adc_raddr_out));
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// channels
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@ -267,9 +270,7 @@ module axi_ad9671 (
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// common processor control
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up_adc_common #(
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.ID(ID)
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) i_up_adc_common (
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up_adc_common #(.ID (ID)) i_up_adc_common (
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.mmcm_rst (),
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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@ -310,9 +311,7 @@ module axi_ad9671 (
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// up bus interface
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up_axi #(
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.ADDRESS_WIDTH (14)
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) i_up_axi (
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up_axi i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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@ -2,6 +2,7 @@
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package require -exact qsys 14.0
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source ../scripts/adi_env.tcl
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source ../scripts/adi_ip_alt.tcl
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set_module_property NAME axi_ad9671
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set_module_property DESCRIPTION "AXI AD9671 Interface"
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@ -23,11 +24,13 @@ add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up
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add_fileset_file up_delay_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_delay_cntrl.v
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add_fileset_file up_adc_common.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v
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add_fileset_file up_adc_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v
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add_fileset_file ad_xcvr_rx_if.v VERILOG PATH $ad_hdl_dir/library/common/ad_xcvr_rx_if.v
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add_fileset_file ad_mem.v VERILOG PATH $ad_hdl_dir/library/common/ad_mem.v
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add_fileset_file axi_ad9671_pnmon.v VERILOG PATH axi_ad9671_pnmon.v
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add_fileset_file axi_ad9671_if.v VERILOG PATH axi_ad9671_if.v
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add_fileset_file axi_ad9671_channel.v VERILOG PATH axi_ad9671_channel.v
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add_fileset_file axi_ad9671.v VERILOG PATH axi_ad9671.v TOP_LEVEL_FILE
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add_fileset_file ad_axi_ip_constr.sdc SDC PATH $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc
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# parameters
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@ -65,7 +68,7 @@ add_interface s_axi axi4lite end
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set_interface_property s_axi associatedClock s_axi_clock
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set_interface_property s_axi associatedReset s_axi_reset
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add_interface_port s_axi s_axi_awvalid awvalid Input 1
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add_interface_port s_axi s_axi_awaddr awaddr Input 14
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add_interface_port s_axi s_axi_awaddr awaddr Input 16
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add_interface_port s_axi s_axi_awprot awprot Input 3
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add_interface_port s_axi s_axi_awready awready Output 1
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add_interface_port s_axi s_axi_wvalid wvalid Input 1
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@ -76,7 +79,7 @@ add_interface_port s_axi s_axi_bvalid bvalid Output 1
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add_interface_port s_axi s_axi_bresp bresp Output 2
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add_interface_port s_axi s_axi_bready bready Input 1
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add_interface_port s_axi s_axi_arvalid arvalid Input 1
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add_interface_port s_axi s_axi_araddr araddr Input 14
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add_interface_port s_axi s_axi_araddr araddr Input 16
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add_interface_port s_axi s_axi_arprot arprot Input 3
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add_interface_port s_axi s_axi_arready arready Output 1
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add_interface_port s_axi s_axi_rvalid rvalid Output 1
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@ -86,31 +89,36 @@ add_interface_port s_axi s_axi_rready rready Input 1
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# transceiver interface
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add_interface xcvr_clk clock end
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add_interface_port xcvr_clk rx_clk clk Input 1
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ad_alt_intf clock rx_clk input 1
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ad_alt_intf signal rx_sof input 4 export
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add_interface xcvr_data conduit end
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set_interface_property xcvr_data associatedClock xcvr_clk
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add_interface_port xcvr_data rx_data data Input 64*QUAD_OR_DUAL_N+64
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add_interface_port xcvr_data rx_sof data_sof Input 1
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add_interface if_rx_data avalon_streaming sink
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add_interface_port if_rx_data rx_data data input 64*QUAD_OR_DUAL_N+64
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add_interface_port if_rx_data rx_valid valid input 1
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add_interface_port if_rx_data rx_ready ready output 1
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set_interface_property if_rx_data associatedClock if_rx_clk
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set_interface_property if_rx_data dataBitsPerSymbol 64
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add_interface xcvr_sync conduit end
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set_interface_property xcvr_sync associatedClock xcvr_clk
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add_interface_port xcvr_sync adc_sync_in sync_in Input 1
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add_interface_port xcvr_sync adc_sync_out sync_out Output 1
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add_interface_port xcvr_sync adc_raddr_in raddr_in Input 4
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add_interface_port xcvr_sync adc_raddr_out raddr_out Output 4
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add_interface if_sync conduit end
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set_interface_property if_sync associatedClock if_clk
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add_interface_port if_sync adc_sync_in sync_in Input 1
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add_interface_port if_sync adc_sync_out sync_out Output 1
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add_interface_port if_sync adc_raddr_in raddr_in Input 4
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add_interface_port if_sync adc_raddr_out raddr_out Output 4
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# dma interface
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add_interface adc_clock clock start
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add_interface_port adc_clock adc_clk clk Output 1
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ad_alt_intf clock adc_clk output 1
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ad_alt_intf reset adc_rst output 1 if_adc_clk
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add_interface adc_dma_if conduit end
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set_interface_property adc_dma_if associatedClock adc_clock
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add_interface_port adc_dma_if adc_valid valid Output 8
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add_interface_port adc_dma_if adc_enable enable Output 8
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add_interface_port adc_dma_if adc_data data Output 128
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add_interface_port adc_dma_if adc_dovf dovf Input 1
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add_interface_port adc_dma_if adc_dunf dunf Input 1
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add_interface adc_ch conduit end
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add_interface_port adc_ch adc_enable enable Output 8
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add_interface_port adc_ch adc_valid valid Output 8
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add_interface_port adc_ch adc_data data Output 128
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set_interface_property adc_ch associatedClock if_rx_clk
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set_interface_property adc_ch associatedReset none
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ad_alt_intf signal adc_dovf input 1 ovf
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ad_alt_intf signal adc_dunf input 1 unf
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@ -34,8 +34,6 @@
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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@ -81,14 +79,15 @@ module axi_ad9671_if (
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// parameters
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parameter QUAD_OR_DUAL_N = 1;
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parameter DEVICE_TYPE = 0;
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parameter ID = 0;
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// jesd interface
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// rx_clk is (line-rate/40)
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input rx_clk;
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input rx_sof;
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input [(64*QUAD_OR_DUAL_N)+63:0] rx_data;
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input [ 3:0] rx_sof;
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input [(64*QUAD_OR_DUAL_N)+63:0] rx_data;
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// adc data output
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@ -122,6 +121,8 @@ module axi_ad9671_if (
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// internal wires
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wire [(2*QUAD_OR_DUAL_N)+1:0] rx_sof_s;
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wire [(64*QUAD_OR_DUAL_N)+63:0] rx_data_s;
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wire [127:0] adc_wdata;
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wire [127:0] adc_rdata;
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wire [ 15:0] adc_data_a_s;
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@ -142,17 +143,16 @@ module axi_ad9671_if (
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reg adc_status = 'd0;
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reg adc_sync_status = 'd0;
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reg rx_sof_d = 'd0;
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reg [ 3:0] adc_waddr = 'd0;
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reg [ 3:0] adc_raddr_out = 'd0;
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reg [ 15:0] adc_data_a;
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reg [ 15:0] adc_data_b;
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reg [ 15:0] adc_data_c;
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reg [ 15:0] adc_data_d;
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reg [ 15:0] adc_data_e;
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reg [ 15:0] adc_data_f;
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reg [ 15:0] adc_data_g;
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reg [ 15:0] adc_data_h;
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reg [ 15:0] adc_data_a = 'd0;
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reg [ 15:0] adc_data_b = 'd0;
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reg [ 15:0] adc_data_c = 'd0;
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reg [ 15:0] adc_data_d = 'd0;
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reg [ 15:0] adc_data_e = 'd0;
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reg [ 15:0] adc_data_f = 'd0;
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reg [ 15:0] adc_data_g = 'd0;
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reg [ 15:0] adc_data_h = 'd0;
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// adc clock & valid
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@ -219,12 +219,12 @@ module axi_ad9671_if (
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always @(posedge rx_clk) begin
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if (QUAD_OR_DUAL_N == 1'b1) begin
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int_valid <= 1'b1;
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int_data <= rx_data;
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int_data <= rx_data_s;
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end else begin
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rx_sof_d <= rx_sof;
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rx_sof_d <= &rx_sof_s;
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int_valid <= rx_sof_d;
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int_data[63:0] <= {rx_data[31:0], int_data[63:32]};
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int_data[127:64] <= {rx_data[63:32], int_data[127:96]};
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int_data[63:0] <= {rx_data_s[31: 0], int_data[ 63:32]};
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int_data[127:64] <= {rx_data_s[63:32], int_data[127:96]};
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end
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end
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@ -245,6 +245,21 @@ module axi_ad9671_if (
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.addrb(adc_raddr_s),
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.doutb(adc_rdata));
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// frame-alignment
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genvar n;
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generate
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for (n = 0; n < ((2*QUAD_OR_DUAL_N)+2); n = n + 1) begin: g_xcvr_if
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ad_xcvr_rx_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_xcvr_if (
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.rx_clk (rx_clk),
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.rx_ip_sof (rx_sof),
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.rx_ip_data (rx_data[((n*32)+31):(n*32)]),
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.rx_sof (rx_sof_s[n]),
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.rx_data (rx_data_s[((n*32)+31):(n*32)]));
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end
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endgenerate
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endmodule
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// ***************************************************************************
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@ -15,6 +15,7 @@ adi_ip_files axi_ad9671 [list \
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"$ad_hdl_dir/library/common/up_adc_common.v" \
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"$ad_hdl_dir/library/common/up_adc_channel.v" \
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"$ad_hdl_dir/library/common/ad_mem.v" \
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"$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \
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"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
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"axi_ad9671_pnmon.v" \
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"axi_ad9671_channel.v" \
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@ -28,6 +29,7 @@ adi_ip_constraints axi_ad9671 [list \
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"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
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"axi_ad9671_constr.xdc" ]
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set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]]
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set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
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set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
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set_property driver_value 0 [ipx::get_ports *sync_in* -of_objects [ipx::current_core]]
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