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altera: adi_jesd204: Disable FPLL phase alignment mode 

Enabling the phase alignment mode of the FPLL seems to break manual
re-calibration, which is required when changing the lane rates. The
calibration seems to select the wrong VCO frequency band and the PLL no
longer locks.

Disable phase alignment mode for now, this has a negative effects on
deterministic latency, but it is better than not working at all.

Waiting for feedback from Altera/Intel on how to make manual re-calibration
work in phase alignment mode.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-08-24 13:12:41 +02:00
parent 72a23eeb71
commit 853342b201
1 changed files with 5 additions and 4 deletions
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9
library/altera/adi_jesd204/adi_jesd204_hw.tcl
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@ -250,16 +250,17 @@ proc jesd204_compose {} {
add_interface ref_clk clock sink
set_interface_property ref_clk EXPORT_OF ref_clock.in_clk
# FIXME: In phase alignment mode manual re-calibration fails
add_instance link_pll altera_xcvr_fpll_a10
set_instance_property link_pll SUPPRESS_ALL_WARNINGS true
set_instance_property link_pll SUPPRESS_ALL_INFO_MESSAGES true
set_instance_parameter_value link_pll {gui_fpll_mode} {0}
set_instance_parameter_value link_pll {gui_reference_clock_frequency} $refclk_frequency
set_instance_parameter_value link_pll {gui_number_of_output_clocks} 2
set_instance_parameter_value link_pll {gui_enable_phase_alignment} 1
set_instance_parameter_value link_pll {gui_number_of_output_clocks} 1
# set_instance_parameter_value link_pll {gui_enable_phase_alignment} 1
set_instance_parameter_value link_pll {gui_desired_outclk0_frequency} $linkclk_frequency
set pfdclk_frequency [get_instance_parameter_value link_pll gui_pfd_frequency]
set_instance_parameter_value link_pll {gui_desired_outclk1_frequency} $pfdclk_frequency
# set pfdclk_frequency [get_instance_parameter_value link_pll gui_pfd_frequency]
# set_instance_parameter_value link_pll {gui_desired_outclk1_frequency} $pfdclk_frequency
set_instance_parameter_value link_pll {enable_pll_reconfig} {1}
set_instance_parameter_value link_pll {set_capability_reg_enable} {1}
set_instance_parameter_value link_pll {set_csr_soft_logic_enable} {1}