alt_ifconv: Remove unused IP
parent
d5e5fcf17a
commit
84bd50d437
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@ -64,7 +64,6 @@ clean:
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$(MAKE) -C intel/avl_adxphy clean
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$(MAKE) -C intel/avl_dacfifo clean
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$(MAKE) -C intel/axi_adxcvr clean
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$(MAKE) -C intel/common/alt_ifconv clean
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$(MAKE) -C intel/common/alt_mem_asym clean
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$(MAKE) -C intel/common/alt_serdes clean
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$(MAKE) -C intel/jesd204_phy clean
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@ -174,7 +173,6 @@ lib:
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$(MAKE) -C intel/avl_adxphy
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$(MAKE) -C intel/avl_dacfifo
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$(MAKE) -C intel/axi_adxcvr
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$(MAKE) -C intel/common/alt_ifconv
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$(MAKE) -C intel/common/alt_mem_asym
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$(MAKE) -C intel/common/alt_serdes
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$(MAKE) -C intel/jesd204_phy
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@ -1,11 +0,0 @@
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := alt_ifconv
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INTEL_DEPS += alt_ifconv.v
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INTEL_DEPS += alt_ifconv_hw.tcl
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include ../../../scripts/library.mk
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@ -1,60 +0,0 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module alt_ifconv #(
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// parameters
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parameter WIDTH = 1,
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parameter INTERFACE_NAME_IN = "input-interface-name",
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parameter INTERFACE_NAME_OUT = "output-interface-name",
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parameter SIGNAL_NAME_IN = "input-signal-name",
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parameter SIGNAL_NAME_OUT = "output-signal-name") (
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// bad tools - ugly stuff
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input [(WIDTH-1):0] din,
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output [(WIDTH-1):0] dout);
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// avoiding qsys signal conflicts
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assign dout = din;
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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@ -1,34 +0,0 @@
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package require qsys
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source ../../../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
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ad_ip_create alt_ifconv {Altera Interface Translator} alt_ifconv_elab
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ad_ip_files alt_ifconv { \
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$ad_hdl_dir/library/intel/common/alt_ifconv/alt_ifconv.v \
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}
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# parameters
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ad_ip_parameter DEVICE_FAMILY STRING {Arria 10}
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ad_ip_parameter WIDTH INTEGER 1
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ad_ip_parameter INTERFACE_NAME_IN STRING {input-interface-name}
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ad_ip_parameter INTERFACE_NAME_OUT STRING {output-interface-name}
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ad_ip_parameter SIGNAL_NAME_IN STRING {input-signal-name}
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ad_ip_parameter SIGNAL_NAME_OUT STRING {output-signal-name}
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proc alt_ifconv_elab {} {
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set m_width [get_parameter_value "WIDTH"]
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set m_if_name_in [get_parameter_value "INTERFACE_NAME_IN"]
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set m_if_name_out [get_parameter_value "INTERFACE_NAME_OUT"]
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set m_sig_name_in [get_parameter_value "SIGNAL_NAME_IN"]
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set m_sig_name_out [get_parameter_value "SIGNAL_NAME_OUT"]
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add_interface $m_if_name_in conduit end
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add_interface_port $m_if_name_in din $m_sig_name_in input $m_width
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add_interface $m_if_name_out conduit end
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add_interface_port $m_if_name_out dout $m_sig_name_out output $m_width
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}
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