imageon: Invert HDMI TX clock
The ADV7511 samples the parallel data bus at the rising edge of sample clock. Generate the clock so that the falling edge is aligned to updating the bus data. This creates larger timing margins on each side of the sampling edge and makes the design more robust. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
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@ -14,6 +14,7 @@ delete_bd_objs [get_bd_ports hdmi_data_e]
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delete_bd_objs [get_bd_ports hdmi_data]
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delete_bd_objs [get_bd_ports hdmi_data]
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set_property CONFIG.EMBEDDED_SYNC {1} [get_bd_cells axi_hdmi_core]
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set_property CONFIG.EMBEDDED_SYNC {1} [get_bd_cells axi_hdmi_core]
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set_property CONFIG.OUT_CLK_POLARITY {1} [get_bd_cells axi_hdmi_core]
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create_bd_port -dir O hdmi_tx_clk
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create_bd_port -dir O hdmi_tx_clk
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create_bd_port -dir O -from 15 -to 0 hdmi_tx_data
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create_bd_port -dir O -from 15 -to 0 hdmi_tx_data
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