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ad9361: adc loopback option

main
Rejeesh Kutty 2014-05-27 12:15:02 -04:00
parent 56ddce1e8c
commit 842cd98b61
7 changed files with 497 additions and 410 deletions
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32
library/axi_ad9361/axi_ad9361.v
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@ -235,6 +235,11 @@ module axi_ad9361 (
wire [ 4:0] delay_rdata_s;
wire delay_ack_t_s;
wire delay_locked_s;
wire adc_valid_pl_s;
wire [11:0] adc_data_pl_i1_s;
wire [11:0] adc_data_pl_q1_s;
wire [11:0] adc_data_pl_i2_s;
wire [11:0] adc_data_pl_q2_s;
wire dac_valid_pl_s;
wire [11:0] dac_data_pl_i1_s;
wire [11:0] dac_data_pl_q1_s;
@ -248,12 +253,16 @@ module axi_ad9361 (
wire dac_pn_enb_i2_s;
wire dac_lb_enb_q2_s;
wire dac_pn_enb_q2_s;
wire adc_lb_enb_i1_s;
wire adc_pn_oos_i1_s;
wire adc_pn_err_i1_s;
wire adc_lb_enb_q1_s;
wire adc_pn_oos_q1_s;
wire adc_pn_err_q1_s;
wire adc_lb_enb_i2_s;
wire adc_pn_oos_i2_s;
wire adc_pn_err_i2_s;
wire adc_lb_enb_q2_s;
wire adc_pn_oos_q2_s;
wire adc_pn_err_q2_s;
wire up_sel_s;
@ -341,17 +350,26 @@ module axi_ad9361 (
.dac_data_in_q1 (dac_data_pl_q1_s),
.dac_data_in_i2 (dac_data_pl_i2_s),
.dac_data_in_q2 (dac_data_pl_q2_s),
.adc_valid (adc_pl_valid_s),
.adc_data_i1 (adc_pl_data_i1_s),
.adc_data_q1 (adc_pl_data_q1_s),
.adc_data_i2 (adc_pl_data_i2_s),
.adc_data_q2 (adc_pl_data_q2_s),
.dac_valid (dac_valid_s),
.dac_data_i1 (dac_data_i1_s),
.dac_data_q1 (dac_data_q1_s),
.dac_data_i2 (dac_data_i2_s),
.dac_data_q2 (dac_data_q2_s),
.adc_lb_enb_i1 (adc_lb_enb_i1_s),
.dac_lb_enb_i1 (dac_lb_enb_i1_s),
.dac_pn_enb_i1 (dac_pn_enb_i1_s),
.adc_lb_enb_q1 (adc_lb_enb_q1_s),
.dac_lb_enb_q1 (dac_lb_enb_q1_s),
.dac_pn_enb_q1 (dac_pn_enb_q1_s),
.adc_lb_enb_i2 (adc_lb_enb_i2_s),
.dac_lb_enb_i2 (dac_lb_enb_i2_s),
.dac_pn_enb_i2 (dac_pn_enb_i2_s),
.adc_lb_enb_q2 (adc_lb_enb_q2_s),
.dac_lb_enb_q2 (dac_lb_enb_q2_s),
.dac_pn_enb_q2 (dac_pn_enb_q2_s),
.adc_pn_oos_i1 (adc_pn_oos_i1_s),
@ -370,19 +388,23 @@ module axi_ad9361 (
.DP_DISABLE (PCORE_ADC_DP_DISABLE))
i_rx (
.adc_clk (clk),
.adc_valid (adc_valid_s),
.adc_valid (adc_pl_valid_s),
.adc_data_i1 (adc_pl_data_i1_s),
.adc_data_q1 (adc_pl_data_q1_s),
.adc_data_i2 (adc_pl_data_i2_s),
.adc_data_q2 (adc_pl_data_q2_s),
.adc_lb_enb_i1 (adc_lb_enb_i1_s),
.adc_pn_oos_i1 (adc_pn_oos_i1_s),
.adc_pn_err_i1 (adc_pn_err_i1_s),
.adc_data_i1 (adc_data_i1_s),
.adc_lb_enb_q1 (adc_lb_enb_q1_s),
.adc_pn_oos_q1 (adc_pn_oos_q1_s),
.adc_pn_err_q1 (adc_pn_err_q1_s),
.adc_data_q1 (adc_data_q1_s),
.adc_lb_enb_i2 (adc_lb_enb_i2_s),
.adc_pn_oos_i2 (adc_pn_oos_i2_s),
.adc_pn_err_i2 (adc_pn_err_i2_s),
.adc_data_i2 (adc_data_i2_s),
.adc_lb_enb_q2 (adc_lb_enb_q2_s),
.adc_pn_oos_q2 (adc_pn_oos_q2_s),
.adc_pn_err_q2 (adc_pn_err_q2_s),
.adc_data_q2 (adc_data_q2_s),
.adc_status (adc_status_s),
.adc_r1_mode (adc_r1_mode_s),
.delay_clk (delay_clk),

1
library/axi_ad9361/axi_ad9361_ip.tcl
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@ -24,6 +24,7 @@ adi_ip_files axi_ad9361 [list \
"$ad_hdl_dir/library/common/up_dac_common.v" \
"$ad_hdl_dir/library/common/up_dac_channel.v" \
"axi_ad9361_dev_if.v" \
"axi_ad9361_pnlb_1.v" \
"axi_ad9361_pnlb.v" \
"axi_ad9361_rx_pnmon.v" \
"axi_ad9361_rx_channel.v" \

474
library/axi_ad9361/axi_ad9361_pnlb.v
View File

@ -43,7 +43,7 @@
module axi_ad9361_pnlb (
// device interface
// interface - inputs
clk,
adc_valid_in,
@ -57,8 +57,13 @@ module axi_ad9361_pnlb (
dac_data_in_i2,
dac_data_in_q2,
// dac outputs
// interface - outputs
adc_valid,
adc_data_i1,
adc_data_q1,
adc_data_i2,
adc_data_q2,
dac_valid,
dac_data_i1,
dac_data_q1,
@ -67,12 +72,16 @@ module axi_ad9361_pnlb (
// control signals
adc_lb_enb_i1,
dac_lb_enb_i1,
dac_pn_enb_i1,
adc_lb_enb_q1,
dac_lb_enb_q1,
dac_pn_enb_q1,
adc_lb_enb_i2,
dac_lb_enb_i2,
dac_pn_enb_i2,
adc_lb_enb_q2,
dac_lb_enb_q2,
dac_pn_enb_q2,
@ -103,6 +112,11 @@ module axi_ad9361_pnlb (
// dac outputs
output adc_valid;
output [11:0] adc_data_i1;
output [11:0] adc_data_q1;
output [11:0] adc_data_i2;
output [11:0] adc_data_q2;
output dac_valid;
output [11:0] dac_data_i1;
output [11:0] dac_data_q1;
@ -111,12 +125,16 @@ module axi_ad9361_pnlb (
// control signals
input adc_lb_enb_i1;
input dac_lb_enb_i1;
input dac_pn_enb_i1;
input adc_lb_enb_q1;
input dac_lb_enb_q1;
input dac_pn_enb_q1;
input adc_lb_enb_i2;
input dac_lb_enb_i2;
input dac_pn_enb_i2;
input adc_lb_enb_q2;
input dac_lb_enb_q2;
input dac_pn_enb_q2;
@ -131,401 +149,71 @@ module axi_ad9361_pnlb (
output adc_pn_oos_q2;
output adc_pn_err_q2;
// internal registers
// instantiations
reg dac_valid_t = 'd0;
reg [23:0] dac_pn_i1 = 'd0;
reg [23:0] dac_pn_q1 = 'd0;
reg [23:0] dac_pn_i2 = 'd0;
reg [23:0] dac_pn_q2 = 'd0;
reg [11:0] dac_lb_i1 = 'd0;
reg [11:0] dac_lb_q1 = 'd0;
reg [11:0] dac_lb_i2 = 'd0;
reg [11:0] dac_lb_q2 = 'd0;
reg dac_valid = 'd0;
reg [11:0] dac_data_i1 = 'd0;
reg [11:0] dac_data_q1 = 'd0;
reg [11:0] dac_data_i2 = 'd0;
reg [11:0] dac_data_q2 = 'd0;
reg adc_valid_t = 'd0;
reg [11:0] adc_data_in_i1_d = 'd0;
reg [11:0] adc_data_in_q1_d = 'd0;
reg [11:0] adc_data_in_i2_d = 'd0;
reg [11:0] adc_data_in_q2_d = 'd0;
reg [23:0] adc_pn_data_i1 = 'd0;
reg [23:0] adc_pn_data_q1 = 'd0;
reg [23:0] adc_pn_data_i2 = 'd0;
reg [23:0] adc_pn_data_q2 = 'd0;
reg adc_pn_err_i1 = 'd0;
reg adc_pn_oos_i1 = 'd0;
reg [ 3:0] adc_pn_oos_count_i1 = 'd0;
reg adc_pn_err_q1 = 'd0;
reg adc_pn_oos_q1 = 'd0;
reg [ 3:0] adc_pn_oos_count_q1 = 'd0;
reg adc_pn_err_i2 = 'd0;
reg adc_pn_oos_i2 = 'd0;
reg [ 3:0] adc_pn_oos_count_i2 = 'd0;
reg adc_pn_err_q2 = 'd0;
reg adc_pn_oos_q2 = 'd0;
reg [ 3:0] adc_pn_oos_count_q2 = 'd0;
axi_ad9361_pnlb_1 #(.PRBS_SEL(0)) i_pnlb_i1 (
.clk (clk),
.adc_valid_in (adc_valid_in),
.adc_data_in (adc_data_in_i1),
.dac_valid_in (dac_valid_in),
.dac_data_in (dac_data_in_i1),
.adc_valid (adc_valid),
.adc_data (adc_data_i1),
.dac_valid (dac_valid),
.dac_data (dac_data_i1),
.adc_lb_enb (adc_lb_enb_i1),
.dac_lb_enb (dac_lb_enb_i1),
.dac_pn_enb (dac_pn_enb_i1),
.adc_pn_oos (adc_pn_oos_i1),
.adc_pn_err (adc_pn_err_i1));
// internal signals
axi_ad9361_pnlb_1 #(.PRBS_SEL(1)) i_pnlb_q1 (
.clk (clk),
.adc_valid_in (adc_valid_in),
.adc_data_in (adc_data_in_q1),
.dac_valid_in (dac_valid_in),
.dac_data_in (dac_data_in_q1),
.adc_valid (),
.adc_data (adc_data_q1),
.dac_valid (),
.dac_data (dac_data_q1),
.adc_lb_enb (adc_lb_enb_q1),
.dac_lb_enb (dac_lb_enb_q1),
.dac_pn_enb (dac_pn_enb_q1),
.adc_pn_oos (adc_pn_oos_q1),
.adc_pn_err (adc_pn_err_q1));
wire dac_valid_t_s;
wire adc_valid_t_s;
wire [23:0] adc_data_in_i1_s;
wire adc_pn_err_i1_s;
wire adc_pn_update_i1_s;
wire adc_pn_match_i1_s;
wire adc_pn_match_i1_z_s;
wire adc_pn_match_i1_d_s;
wire [23:0] adc_pn_data_i1_s;
wire [23:0] adc_data_in_q1_s;
wire adc_pn_err_q1_s;
wire adc_pn_update_q1_s;
wire adc_pn_match_q1_s;
wire adc_pn_match_q1_z_s;
wire adc_pn_match_q1_d_s;
wire [23:0] adc_pn_data_q1_s;
wire [23:0] adc_data_in_i2_s;
wire adc_pn_err_i2_s;
wire adc_pn_update_i2_s;
wire adc_pn_match_i2_s;
wire adc_pn_match_i2_z_s;
wire adc_pn_match_i2_d_s;
wire [23:0] adc_pn_data_i2_s;
wire [23:0] adc_data_in_q2_s;
wire adc_pn_err_q2_s;
wire adc_pn_update_q2_s;
wire adc_pn_match_q2_s;
wire adc_pn_match_q2_z_s;
wire adc_pn_match_q2_d_s;
wire [23:0] adc_pn_data_q2_s;
axi_ad9361_pnlb_1 #(.PRBS_SEL(2)) i_pnlb_i2 (
.clk (clk),
.adc_valid_in (adc_valid_in),
.adc_data_in (adc_data_in_i2),
.dac_valid_in (dac_valid_in),
.dac_data_in (dac_data_in_i2),
.adc_valid (),
.adc_data (adc_data_i2),
.dac_valid (),
.dac_data (dac_data_i2),
.adc_lb_enb (adc_lb_enb_i2),
.dac_lb_enb (dac_lb_enb_i2),
.dac_pn_enb (dac_pn_enb_i2),
.adc_pn_oos (adc_pn_oos_i2),
.adc_pn_err (adc_pn_err_i2));
// prbs-9 function
function [23:0] pn09;
input [23:0] din;
reg [23:0] dout;
begin
dout[23] = din[ 8] ^ din[ 4];
dout[22] = din[ 7] ^ din[ 3];
dout[21] = din[ 6] ^ din[ 2];
dout[20] = din[ 5] ^ din[ 1];
dout[19] = din[ 4] ^ din[ 0];
dout[18] = din[ 3] ^ din[ 8] ^ din[ 4];
dout[17] = din[ 2] ^ din[ 7] ^ din[ 3];
dout[16] = din[ 1] ^ din[ 6] ^ din[ 2];
dout[15] = din[ 0] ^ din[ 5] ^ din[ 1];
dout[14] = din[ 8] ^ din[ 0];
dout[13] = din[ 7] ^ din[ 8] ^ din[ 4];
dout[12] = din[ 6] ^ din[ 7] ^ din[ 3];
dout[11] = din[ 5] ^ din[ 6] ^ din[ 2];
dout[10] = din[ 4] ^ din[ 5] ^ din[ 1];
dout[ 9] = din[ 3] ^ din[ 4] ^ din[ 0];
dout[ 8] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[ 7] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[ 6] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[ 5] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[ 4] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
dout[ 3] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
dout[ 2] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[ 1] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[ 0] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
pn09 = dout;
end
endfunction
// prbs-11 function
function [23:0] pn11;
input [23:0] din;
reg [23:0] dout;
begin
dout[23] = din[10] ^ din[ 8];
dout[22] = din[ 9] ^ din[ 7];
dout[21] = din[ 8] ^ din[ 6];
dout[20] = din[ 7] ^ din[ 5];
dout[19] = din[ 6] ^ din[ 4];
dout[18] = din[ 5] ^ din[ 3];
dout[17] = din[ 4] ^ din[ 2];
dout[16] = din[ 3] ^ din[ 1];
dout[15] = din[ 2] ^ din[ 0];
dout[14] = din[ 1] ^ din[10] ^ din[ 8];
dout[13] = din[ 0] ^ din[ 9] ^ din[ 7];
dout[12] = din[10] ^ din[ 6];
dout[11] = din[ 9] ^ din[ 5];
dout[10] = din[ 8] ^ din[ 4];
dout[ 9] = din[ 7] ^ din[ 3];
dout[ 8] = din[ 6] ^ din[ 2];
dout[ 7] = din[ 5] ^ din[ 1];
dout[ 6] = din[ 4] ^ din[ 0];
dout[ 5] = din[ 3] ^ din[10] ^ din[ 8];
dout[ 4] = din[ 2] ^ din[ 9] ^ din[ 7];
dout[ 3] = din[ 1] ^ din[ 8] ^ din[ 6];
dout[ 2] = din[ 0] ^ din[ 7] ^ din[ 5];
dout[ 1] = din[10] ^ din[ 6] ^ din[ 8] ^ din[ 4];
dout[ 0] = din[ 9] ^ din[ 5] ^ din[ 7] ^ din[ 3];
pn11 = dout;
end
endfunction
// prbs-15 function
function [23:0] pn15;
input [23:0] din;
reg [23:0] dout;
begin
dout[23] = din[14] ^ din[13];
dout[22] = din[13] ^ din[12];
dout[21] = din[12] ^ din[11];
dout[20] = din[11] ^ din[10];
dout[19] = din[10] ^ din[ 9];
dout[18] = din[ 9] ^ din[ 8];
dout[17] = din[ 8] ^ din[ 7];
dout[16] = din[ 7] ^ din[ 6];
dout[15] = din[ 6] ^ din[ 5];
dout[14] = din[ 5] ^ din[ 4];
dout[13] = din[ 4] ^ din[ 3];
dout[12] = din[ 3] ^ din[ 2];
dout[11] = din[ 2] ^ din[ 1];
dout[10] = din[ 1] ^ din[ 0];
dout[ 9] = din[ 0] ^ din[14] ^ din[13];
dout[ 8] = din[14] ^ din[12];
dout[ 7] = din[13] ^ din[11];
dout[ 6] = din[12] ^ din[10];
dout[ 5] = din[11] ^ din[ 9];
dout[ 4] = din[10] ^ din[ 8];
dout[ 3] = din[ 9] ^ din[ 7];
dout[ 2] = din[ 8] ^ din[ 6];
dout[ 1] = din[ 7] ^ din[ 5];
dout[ 0] = din[ 6] ^ din[ 4];
pn15 = dout;
end
endfunction
// prbs-20 function
function [23:0] pn20;
input [23:0] din;
reg [23:0] dout;
begin
dout[23] = din[19] ^ din[ 2];
dout[22] = din[18] ^ din[ 1];
dout[21] = din[17] ^ din[ 0];
dout[20] = din[16] ^ din[19] ^ din[ 2];
dout[19] = din[15] ^ din[18] ^ din[ 1];
dout[18] = din[14] ^ din[17] ^ din[ 0];
dout[17] = din[13] ^ din[16] ^ din[19] ^ din[ 2];
dout[16] = din[12] ^ din[15] ^ din[18] ^ din[ 1];
dout[15] = din[11] ^ din[14] ^ din[17] ^ din[ 0];
dout[14] = din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
dout[13] = din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
dout[12] = din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
dout[11] = din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
dout[10] = din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
dout[ 9] = din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
dout[ 8] = din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
dout[ 7] = din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
dout[ 6] = din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
dout[ 5] = din[ 1] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
dout[ 4] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
dout[ 3] = din[19] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
dout[ 2] = din[18] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
dout[ 1] = din[17] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
dout[ 0] = din[16] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
pn20 = dout;
end
endfunction
// prbs generators run at 24bits wide
assign dac_valid_t_s = dac_valid_in & dac_valid_t;
always @(posedge clk) begin
if (dac_valid_in == 1'b1) begin
dac_valid_t <= ~dac_valid_t;
end
if (dac_pn_enb_i1 == 1'b0) begin
dac_pn_i1 <= 24'hffffff;
end else if (dac_valid_t_s == 1'b1) begin
dac_pn_i1 <= pn09(dac_pn_i1);
end
if (dac_pn_enb_q1 == 1'b0) begin
dac_pn_q1 <= 24'hffffff;
end else if (dac_valid_t_s == 1'b1) begin
dac_pn_q1 <= pn11(dac_pn_q1);
end
if (dac_pn_enb_i2 == 1'b0) begin
dac_pn_i2 <= 24'hffffff;
end else if (dac_valid_t_s == 1'b1) begin
dac_pn_i2 <= pn15(dac_pn_i2);
end
if (dac_pn_enb_q2 == 1'b0) begin
dac_pn_q2 <= 24'hffffff;
end else if (dac_valid_t_s == 1'b1) begin
dac_pn_q2 <= pn20(dac_pn_q2);
end
end
// hold adc data for loopback, it is assumed that there is a one to one mapping
// of receive and transmit (the rates are the same).
always @(posedge clk) begin
if (adc_valid_in == 1'b1) begin
dac_lb_i1 <= adc_data_in_i1;
dac_lb_q1 <= adc_data_in_q1;
dac_lb_i2 <= adc_data_in_i2;
dac_lb_q2 <= adc_data_in_q2;
end
end
// dac outputs-
always @(posedge clk) begin
dac_valid <= dac_valid_in;
if (dac_pn_enb_i1 == 1'b1) begin
if (dac_valid_t == 1'b1) begin
dac_data_i1 <= dac_pn_i1[11:0];
end else begin
dac_data_i1 <= dac_pn_i1[23:12];
end
end else if (dac_lb_enb_i1 == 1'b1) begin
dac_data_i1 <= dac_lb_i1;
end else begin
dac_data_i1 <= dac_data_in_i1;
end
if (dac_pn_enb_q1 == 1'b1) begin
if (dac_valid_t == 1'b1) begin
dac_data_q1 <= dac_pn_q1[11:0];
end else begin
dac_data_q1 <= dac_pn_q1[23:12];
end
end else if (dac_lb_enb_q1 == 1'b1) begin
dac_data_q1 <= dac_lb_q1;
end else begin
dac_data_q1 <= dac_data_in_q1;
end
if (dac_pn_enb_i2 == 1'b1) begin
if (dac_valid_t == 1'b1) begin
dac_data_i2 <= dac_pn_i2[11:0];
end else begin
dac_data_i2 <= dac_pn_i2[23:12];
end
end else if (dac_lb_enb_i2 == 1'b1) begin
dac_data_i2 <= dac_lb_i2;
end else begin
dac_data_i2 <= dac_data_in_i2;
end
if (dac_pn_enb_q2 == 1'b1) begin
if (dac_valid_t == 1'b1) begin
dac_data_q2 <= dac_pn_q2[11:0];
end else begin
dac_data_q2 <= dac_pn_q2[23:12];
end
end else if (dac_lb_enb_q2 == 1'b1) begin
dac_data_q2 <= dac_lb_q2;
end else begin
dac_data_q2 <= dac_data_in_q2;
end
end
// adc pn monitoring
assign adc_valid_t_s = adc_valid_in & adc_valid_t;
assign adc_data_in_i1_s = {adc_data_in_i1_d, adc_data_in_i1};
assign adc_pn_err_i1_s = ~(adc_pn_oos_i1 | adc_pn_match_i1_s);
assign adc_pn_update_i1_s = ~(adc_pn_oos_i1 ^ adc_pn_match_i1_s);
assign adc_pn_match_i1_s = adc_pn_match_i1_d_s & adc_pn_match_i1_z_s;
assign adc_pn_match_i1_z_s = (adc_data_in_i1_s == 24'd0) ? 1'b0 : 1'b1;
assign adc_pn_match_i1_d_s = (adc_data_in_i1_s == adc_pn_data_i1) ? 1'b1 : 1'b0;
assign adc_pn_data_i1_s = (adc_pn_oos_i1 == 1'b1) ? adc_data_in_i1_s : adc_pn_data_i1;
assign adc_data_in_q1_s = {adc_data_in_q1_d, adc_data_in_q1};
assign adc_pn_err_q1_s = ~(adc_pn_oos_q1 | adc_pn_match_q1_s);
assign adc_pn_update_q1_s = ~(adc_pn_oos_q1 ^ adc_pn_match_q1_s);
assign adc_pn_match_q1_s = adc_pn_match_q1_d_s & adc_pn_match_q1_z_s;
assign adc_pn_match_q1_z_s = (adc_data_in_q1_s == 24'd0) ? 1'b0 : 1'b1;
assign adc_pn_match_q1_d_s = (adc_data_in_q1_s == adc_pn_data_q1) ? 1'b1 : 1'b0;
assign adc_pn_data_q1_s = (adc_pn_oos_q1 == 1'b1) ? adc_data_in_q1_s : adc_pn_data_q1;
assign adc_data_in_i2_s = {adc_data_in_i2_d, adc_data_in_i2};
assign adc_pn_err_i2_s = ~(adc_pn_oos_i2 | adc_pn_match_i2_s);
assign adc_pn_update_i2_s = ~(adc_pn_oos_i2 ^ adc_pn_match_i2_s);
assign adc_pn_match_i2_s = adc_pn_match_i2_d_s & adc_pn_match_i2_z_s;
assign adc_pn_match_i2_z_s = (adc_data_in_i2_s == 24'd0) ? 1'b0 : 1'b1;
assign adc_pn_match_i2_d_s = (adc_data_in_i2_s == adc_pn_data_i2) ? 1'b1 : 1'b0;
assign adc_pn_data_i2_s = (adc_pn_oos_i2 == 1'b1) ? adc_data_in_i2_s : adc_pn_data_i2;
assign adc_data_in_q2_s = {adc_data_in_q2_d, adc_data_in_q2};
assign adc_pn_err_q2_s = ~(adc_pn_oos_q2 | adc_pn_match_q2_s);
assign adc_pn_update_q2_s = ~(adc_pn_oos_q2 ^ adc_pn_match_q2_s);
assign adc_pn_match_q2_s = adc_pn_match_q2_d_s & adc_pn_match_q2_z_s;
assign adc_pn_match_q2_z_s = (adc_data_in_q2_s == 24'd0) ? 1'b0 : 1'b1;
assign adc_pn_match_q2_d_s = (adc_data_in_q2_s == adc_pn_data_q2) ? 1'b1 : 1'b0;
assign adc_pn_data_q2_s = (adc_pn_oos_q2 == 1'b1) ? adc_data_in_q2_s : adc_pn_data_q2;
// adc pn running sequence
always @(posedge clk) begin
if (adc_valid_in == 1'b1) begin
adc_valid_t <= ~adc_valid_t;
adc_data_in_i1_d <= adc_data_in_i1;
adc_data_in_q1_d <= adc_data_in_q1;
adc_data_in_i2_d <= adc_data_in_i2;
adc_data_in_q2_d <= adc_data_in_q2;
end
if (adc_valid_t_s == 1'b1) begin
adc_pn_data_i1 <= pn09(adc_pn_data_i1_s);
adc_pn_data_q1 <= pn11(adc_pn_data_q1_s);
adc_pn_data_i2 <= pn15(adc_pn_data_i2_s);
adc_pn_data_q2 <= pn20(adc_pn_data_q2_s);
end
end
// pn oos and counters (16 to clear and set).
always @(posedge clk) begin
if (adc_valid_t_s == 1'b1) begin
adc_pn_err_i1 <= adc_pn_err_i1_s;
if ((adc_pn_update_i1_s == 1'b1) && (adc_pn_oos_count_i1 >= 15)) begin
adc_pn_oos_i1 <= ~adc_pn_oos_i1;
end
if (adc_pn_update_i1_s == 1'b1) begin
adc_pn_oos_count_i1 <= adc_pn_oos_count_i1 + 1'b1;
end else begin
adc_pn_oos_count_i1 <= 'd0;
end
adc_pn_err_q1 <= adc_pn_err_q1_s;
if ((adc_pn_update_q1_s == 1'b1) && (adc_pn_oos_count_q1 >= 15)) begin
adc_pn_oos_q1 <= ~adc_pn_oos_q1;
end
if (adc_pn_update_q1_s == 1'b1) begin
adc_pn_oos_count_q1 <= adc_pn_oos_count_q1 + 1'b1;
end else begin
adc_pn_oos_count_q1 <= 'd0;
end
adc_pn_err_i2 <= adc_pn_err_i2_s;
if ((adc_pn_update_i2_s == 1'b1) && (adc_pn_oos_count_i2 >= 15)) begin
adc_pn_oos_i2 <= ~adc_pn_oos_i2;
end
if (adc_pn_update_i2_s == 1'b1) begin
adc_pn_oos_count_i2 <= adc_pn_oos_count_i2 + 1'b1;
end else begin
adc_pn_oos_count_i2 <= 'd0;
end
adc_pn_err_q2 <= adc_pn_err_q2_s;
if ((adc_pn_update_q2_s == 1'b1) && (adc_pn_oos_count_q2 >= 15)) begin
adc_pn_oos_q2 <= ~adc_pn_oos_q2;
end
if (adc_pn_update_q2_s == 1'b1) begin
adc_pn_oos_count_q2 <= adc_pn_oos_count_q2 + 1'b1;
end else begin
adc_pn_oos_count_q2 <= 'd0;
end
end
end
axi_ad9361_pnlb_1 #(.PRBS_SEL(3)) i_pnlb_q2 (
.clk (clk),
.adc_valid_in (adc_valid_in),
.adc_data_in (adc_data_in_q2),
.dac_valid_in (dac_valid_in),
.dac_data_in (dac_data_in_q2),
.adc_valid (),
.adc_data (adc_data_q2),
.dac_valid (),
.dac_data (dac_data_q2),
.adc_lb_enb (adc_lb_enb_q2),
.dac_lb_enb (dac_lb_enb_q2),
.dac_pn_enb (dac_pn_enb_q2),
.adc_pn_oos (adc_pn_oos_q2),
.adc_pn_err (adc_pn_err_q2));
endmodule

354
library/axi_ad9361/axi_ad9361_pnlb_1.v Executable file
View File

@ -0,0 +1,354 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This interface includes both the transmit and receive components -
// They both uses the same clock (sourced from the receiving side).
`timescale 1ns/100ps
module axi_ad9361_pnlb_1 (
// device interface
clk,
adc_valid_in,
adc_data_in,
dac_valid_in,
dac_data_in,
// dac outputs
adc_valid,
adc_data,
dac_valid,
dac_data,
// control signals
adc_lb_enb,
dac_lb_enb,
dac_pn_enb,
// status signals
adc_pn_oos,
adc_pn_err);
// parameters
parameter PRBS_SEL = 0;
localparam PRBS_P09 = 0;
localparam PRBS_P11 = 1;
localparam PRBS_P15 = 2;
localparam PRBS_P20 = 3;
// device interface
input clk;
input adc_valid_in;
input [11:0] adc_data_in;
input dac_valid_in;
input [11:0] dac_data_in;
// dac outputs
output adc_valid;
output [11:0] adc_data;
output dac_valid;
output [11:0] dac_data;
// control signals
input adc_lb_enb;
input dac_lb_enb;
input dac_pn_enb;
// status signals
output adc_pn_oos;
output adc_pn_err;
// internal registers
reg dac_valid_t = 'd0;
reg [23:0] dac_pn = 'd0;
reg [11:0] dac_lb = 'd0;
reg dac_valid = 'd0;
reg [11:0] dac_data = 'd0;
reg [11:0] adc_lb = 'd0;
reg adc_valid = 'd0;
reg [11:0] adc_data = 'd0;
reg adc_valid_t = 'd0;
reg [11:0] adc_data_in_d = 'd0;
reg [23:0] adc_pn_data = 'd0;
reg adc_pn_err = 'd0;
reg adc_pn_oos = 'd0;
reg [ 3:0] adc_pn_oos_count = 'd0;
// internal signals
wire dac_valid_t_s;
wire adc_valid_t_s;
wire [23:0] adc_data_in_s;
wire adc_pn_err_s;
wire adc_pn_update_s;
wire adc_pn_match_s;
wire adc_pn_match_z_s;
wire adc_pn_match_d_s;
wire [23:0] adc_pn_data_s;
// prbs functions
function [23:0] pn;
input [23:0] din;
reg [23:0] dout;
begin
case (PRBS_SEL)
PRBS_P09: begin
dout[23] = din[ 8] ^ din[ 4];
dout[22] = din[ 7] ^ din[ 3];
dout[21] = din[ 6] ^ din[ 2];
dout[20] = din[ 5] ^ din[ 1];
dout[19] = din[ 4] ^ din[ 0];
dout[18] = din[ 3] ^ din[ 8] ^ din[ 4];
dout[17] = din[ 2] ^ din[ 7] ^ din[ 3];
dout[16] = din[ 1] ^ din[ 6] ^ din[ 2];
dout[15] = din[ 0] ^ din[ 5] ^ din[ 1];
dout[14] = din[ 8] ^ din[ 0];
dout[13] = din[ 7] ^ din[ 8] ^ din[ 4];
dout[12] = din[ 6] ^ din[ 7] ^ din[ 3];
dout[11] = din[ 5] ^ din[ 6] ^ din[ 2];
dout[10] = din[ 4] ^ din[ 5] ^ din[ 1];
dout[ 9] = din[ 3] ^ din[ 4] ^ din[ 0];
dout[ 8] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[ 7] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[ 6] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[ 5] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[ 4] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
dout[ 3] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
dout[ 2] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[ 1] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[ 0] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
end
PRBS_P11: begin
dout[23] = din[10] ^ din[ 8];
dout[22] = din[ 9] ^ din[ 7];
dout[21] = din[ 8] ^ din[ 6];
dout[20] = din[ 7] ^ din[ 5];
dout[19] = din[ 6] ^ din[ 4];
dout[18] = din[ 5] ^ din[ 3];
dout[17] = din[ 4] ^ din[ 2];
dout[16] = din[ 3] ^ din[ 1];
dout[15] = din[ 2] ^ din[ 0];
dout[14] = din[ 1] ^ din[10] ^ din[ 8];
dout[13] = din[ 0] ^ din[ 9] ^ din[ 7];
dout[12] = din[10] ^ din[ 6];
dout[11] = din[ 9] ^ din[ 5];
dout[10] = din[ 8] ^ din[ 4];
dout[ 9] = din[ 7] ^ din[ 3];
dout[ 8] = din[ 6] ^ din[ 2];
dout[ 7] = din[ 5] ^ din[ 1];
dout[ 6] = din[ 4] ^ din[ 0];
dout[ 5] = din[ 3] ^ din[10] ^ din[ 8];
dout[ 4] = din[ 2] ^ din[ 9] ^ din[ 7];
dout[ 3] = din[ 1] ^ din[ 8] ^ din[ 6];
dout[ 2] = din[ 0] ^ din[ 7] ^ din[ 5];
dout[ 1] = din[10] ^ din[ 6] ^ din[ 8] ^ din[ 4];
dout[ 0] = din[ 9] ^ din[ 5] ^ din[ 7] ^ din[ 3];
end
PRBS_P15: begin
dout[23] = din[14] ^ din[13];
dout[22] = din[13] ^ din[12];
dout[21] = din[12] ^ din[11];
dout[20] = din[11] ^ din[10];
dout[19] = din[10] ^ din[ 9];
dout[18] = din[ 9] ^ din[ 8];
dout[17] = din[ 8] ^ din[ 7];
dout[16] = din[ 7] ^ din[ 6];
dout[15] = din[ 6] ^ din[ 5];
dout[14] = din[ 5] ^ din[ 4];
dout[13] = din[ 4] ^ din[ 3];
dout[12] = din[ 3] ^ din[ 2];
dout[11] = din[ 2] ^ din[ 1];
dout[10] = din[ 1] ^ din[ 0];
dout[ 9] = din[ 0] ^ din[14] ^ din[13];
dout[ 8] = din[14] ^ din[12];
dout[ 7] = din[13] ^ din[11];
dout[ 6] = din[12] ^ din[10];
dout[ 5] = din[11] ^ din[ 9];
dout[ 4] = din[10] ^ din[ 8];
dout[ 3] = din[ 9] ^ din[ 7];
dout[ 2] = din[ 8] ^ din[ 6];
dout[ 1] = din[ 7] ^ din[ 5];
dout[ 0] = din[ 6] ^ din[ 4];
end
PRBS_P20: begin
dout[23] = din[19] ^ din[ 2];
dout[22] = din[18] ^ din[ 1];
dout[21] = din[17] ^ din[ 0];
dout[20] = din[16] ^ din[19] ^ din[ 2];
dout[19] = din[15] ^ din[18] ^ din[ 1];
dout[18] = din[14] ^ din[17] ^ din[ 0];
dout[17] = din[13] ^ din[16] ^ din[19] ^ din[ 2];
dout[16] = din[12] ^ din[15] ^ din[18] ^ din[ 1];
dout[15] = din[11] ^ din[14] ^ din[17] ^ din[ 0];
dout[14] = din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
dout[13] = din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
dout[12] = din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
dout[11] = din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
dout[10] = din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
dout[ 9] = din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
dout[ 8] = din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
dout[ 7] = din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
dout[ 6] = din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
dout[ 5] = din[ 1] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
dout[ 4] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
dout[ 3] = din[19] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
dout[ 2] = din[18] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
dout[ 1] = din[17] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
dout[ 0] = din[16] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
end
endcase
pn = dout;
end
endfunction
// prbs generators run at 24bits wide
assign dac_valid_t_s = dac_valid_in & dac_valid_t;
always @(posedge clk) begin
if (dac_valid_in == 1'b1) begin
dac_valid_t <= ~dac_valid_t;
end
if (dac_pn_enb == 1'b0) begin
dac_pn <= 24'hffffff;
end else if (dac_valid_t_s == 1'b1) begin
dac_pn <= pn(dac_pn);
end
end
// hold adc data for loopback, it is assumed that there is a one to one mapping
// of receive and transmit (the rates are the same).
always @(posedge clk) begin
if (dac_valid_in == 1'b1) begin
dac_lb <= adc_data_in;
end
end
// dac outputs-
always @(posedge clk) begin
dac_valid <= dac_valid_in;
if (dac_pn_enb == 1'b1) begin
if (dac_valid_t == 1'b1) begin
dac_data <= dac_pn[11:0];
end else begin
dac_data <= dac_pn[23:12];
end
end else if (dac_lb_enb == 1'b1) begin
dac_data <= dac_lb;
end else begin
dac_data <= dac_data_in;
end
end
// hold dac data for loopback, it is assumed that there is a one to one mapping
// of receive and transmit (the rates are the same).
always @(posedge clk) begin
if (adc_valid_in == 1'b1) begin
adc_lb <= dac_data_in;
end
end
// adc outputs-
always @(posedge clk) begin
adc_valid <= adc_valid_in;
if (adc_lb_enb == 1'b1) begin
adc_data <= adc_lb;
end else begin
adc_data <= adc_data_in;
end
end
// adc pn monitoring
assign adc_valid_t_s = adc_valid_in & adc_valid_t;
assign adc_data_in_s = {adc_data_in_d, adc_data_in};
assign adc_pn_err_s = ~(adc_pn_oos | adc_pn_match_s);
assign adc_pn_update_s = ~(adc_pn_oos ^ adc_pn_match_s);
assign adc_pn_match_s = adc_pn_match_d_s & adc_pn_match_z_s;
assign adc_pn_match_z_s = (adc_data_in_s == 24'd0) ? 1'b0 : 1'b1;
assign adc_pn_match_d_s = (adc_data_in_s == adc_pn_data) ? 1'b1 : 1'b0;
assign adc_pn_data_s = (adc_pn_oos == 1'b1) ? adc_data_in_s : adc_pn_data;
// adc pn running sequence
always @(posedge clk) begin
if (adc_valid_in == 1'b1) begin
adc_valid_t <= ~adc_valid_t;
adc_data_in_d <= adc_data_in;
end
if (adc_valid_t_s == 1'b1) begin
adc_pn_data <= pn(adc_pn_data_s);
end
end
// pn oos and counters (16 to clear and set).
always @(posedge clk) begin
if (adc_valid_t_s == 1'b1) begin
adc_pn_err <= adc_pn_err_s;
if ((adc_pn_update_s == 1'b1) && (adc_pn_oos_count >= 15)) begin
adc_pn_oos <= ~adc_pn_oos;
end
if (adc_pn_update_s == 1'b1) begin
adc_pn_oos_count <= adc_pn_oos_count + 1'b1;
end else begin
adc_pn_oos_count <= 'd0;
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************

28
library/axi_ad9361/axi_ad9361_rx.v
View File

@ -46,18 +46,22 @@ module axi_ad9361_rx (
adc_clk,
adc_valid,
adc_data_i1,
adc_data_q1,
adc_data_i2,
adc_data_q2,
adc_lb_enb_i1,
adc_pn_oos_i1,
adc_pn_err_i1,
adc_data_i1,
adc_lb_enb_q1,
adc_pn_oos_q1,
adc_pn_err_q1,
adc_data_q1,
adc_lb_enb_i2,
adc_pn_oos_i2,
adc_pn_err_i2,
adc_data_i2,
adc_lb_enb_q2,
adc_pn_oos_q2,
adc_pn_err_q2,
adc_data_q2,
adc_status,
adc_r1_mode,
@ -111,18 +115,22 @@ module axi_ad9361_rx (
input adc_clk;
input adc_valid;
input [11:0] adc_data_i1;
input [11:0] adc_data_q1;
input [11:0] adc_data_i2;
input [11:0] adc_data_q2;
output adc_lb_enb_i1;
input adc_pn_oos_i1;
input adc_pn_err_i1;
input [11:0] adc_data_i1;
output adc_lb_enb_q1;
input adc_pn_oos_q1;
input adc_pn_err_q1;
input [11:0] adc_data_q1;
output adc_lb_enb_i2;
input adc_pn_oos_i2;
input adc_pn_err_i2;
input [11:0] adc_data_i2;
output adc_lb_enb_q2;
input adc_pn_oos_q2;
input adc_pn_err_q2;
input [11:0] adc_data_q2;
input adc_status;
output adc_r1_mode;
@ -543,6 +551,7 @@ module axi_ad9361_rx (
.adc_iqcor_valid (adc_iqcor_valid_0_s),
.adc_iqcor_data (adc_iqcor_data_0_s),
.adc_enable (adc_enable_0_s),
.adc_lb_enb (adc_lb_enb_i1),
.up_adc_pn_err (up_adc_pn_err_0_s),
.up_adc_pn_oos (up_adc_pn_oos_0_s),
.up_adc_or (up_adc_or_0_s),
@ -579,6 +588,7 @@ module axi_ad9361_rx (
.adc_iqcor_valid (adc_iqcor_valid_1_s),
.adc_iqcor_data (adc_iqcor_data_1_s),
.adc_enable (adc_enable_1_s),
.adc_lb_enb (adc_lb_enb_q1),
.up_adc_pn_err (up_adc_pn_err_1_s),
.up_adc_pn_oos (up_adc_pn_oos_1_s),
.up_adc_or (up_adc_or_1_s),
@ -615,6 +625,7 @@ module axi_ad9361_rx (
.adc_iqcor_valid (adc_iqcor_valid_2_s),
.adc_iqcor_data (adc_iqcor_data_2_s),
.adc_enable (adc_enable_2_s),
.adc_lb_enb (adc_lb_enb_i2),
.up_adc_pn_err (up_adc_pn_err_2_s),
.up_adc_pn_oos (up_adc_pn_oos_2_s),
.up_adc_or (up_adc_or_2_s),
@ -651,6 +662,7 @@ module axi_ad9361_rx (
.adc_iqcor_valid (adc_iqcor_valid_3_s),
.adc_iqcor_data (adc_iqcor_data_3_s),
.adc_enable (adc_enable_3_s),
.adc_lb_enb (adc_lb_enb_q2),
.up_adc_pn_err (up_adc_pn_err_3_s),
.up_adc_pn_oos (up_adc_pn_oos_3_s),
.up_adc_or (up_adc_or_3_s),

3
library/axi_ad9361/axi_ad9361_rx_channel.v
View File

@ -64,6 +64,7 @@ module axi_ad9361_rx_channel (
adc_iqcor_valid,
adc_iqcor_data,
adc_enable,
adc_lb_enb,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
@ -107,6 +108,7 @@ module axi_ad9361_rx_channel (
output adc_iqcor_valid;
output [15:0] adc_iqcor_data;
output adc_enable;
input adc_lb_enb;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
@ -220,6 +222,7 @@ module axi_ad9361_rx_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_lb_enb (adc_lb_enb),
.adc_pn_sel (adc_pn_sel_s),
.adc_iqcor_enb (adc_iqcor_enb_s),
.adc_dcfilt_enb (adc_dcfilt_enb_s),

15
library/common/up_adc_channel.v
View File

@ -46,6 +46,7 @@ module up_adc_channel (
adc_clk,
adc_rst,
adc_enable,
adc_lb_enb,
adc_pn_sel,
adc_iqcor_enb,
adc_dcfilt_enb,
@ -101,6 +102,7 @@ module up_adc_channel (
input adc_clk;
input adc_rst;
output adc_enable;
output adc_lb_enb;
output adc_pn_sel;
output adc_iqcor_enb;
output adc_dcfilt_enb;
@ -149,6 +151,7 @@ module up_adc_channel (
// internal registers
reg up_adc_lb_enb = 'd0;
reg up_adc_pn_sel = 'd0;
reg up_adc_iqcor_enb = 'd0;
reg up_adc_dcfilt_enb = 'd0;
@ -191,6 +194,7 @@ module up_adc_channel (
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_adc_lb_enb <= 'd0;
up_adc_pn_sel <= 'd0;
up_adc_iqcor_enb <= 'd0;
up_adc_dcfilt_enb <= 'd0;
@ -215,6 +219,7 @@ module up_adc_channel (
up_usr_decimation_n <= 'd0;
end else begin
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h0)) begin
up_adc_lb_enb <= up_wdata[11];
up_adc_pn_sel <= up_wdata[10];
up_adc_iqcor_enb <= up_wdata[9];
up_adc_dcfilt_enb <= up_wdata[8];
@ -271,7 +276,7 @@ module up_adc_channel (
up_ack <= up_sel_s;
if (up_sel_s == 1'b1) begin
case (up_addr[3:0])
4'h0: up_rdata <= {21'd0, up_adc_pn_sel, up_adc_iqcor_enb, up_adc_dcfilt_enb,
4'h0: up_rdata <= {20'd0, up_adc_lb_enb, up_adc_pn_sel, up_adc_iqcor_enb, up_adc_dcfilt_enb,
1'd0, up_adc_dfmt_se, up_adc_dfmt_type, up_adc_dfmt_enable,
2'd0, up_adc_pn_type, up_adc_enable};
4'h1: up_rdata <= {29'd0, up_adc_pn_err, up_adc_pn_oos, up_adc_or};
@ -291,10 +296,11 @@ module up_adc_channel (
// adc control & status
up_xfer_cntrl #(.DATA_WIDTH(72)) i_adc_xfer_cntrl (
up_xfer_cntrl #(.DATA_WIDTH(73)) i_adc_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_adc_pn_sel,
.up_data_cntrl ({ up_adc_lb_enb,
up_adc_pn_sel,
up_adc_iqcor_enb,
up_adc_dcfilt_enb,
up_adc_dfmt_se,
@ -308,7 +314,8 @@ module up_adc_channel (
up_adc_iqcor_coeff_2}),
.d_rst (adc_rst),
.d_clk (adc_clk),
.d_data_cntrl ({ adc_pn_sel,
.d_data_cntrl ({ adc_lb_enb,
adc_pn_sel,
adc_iqcor_enb,
adc_dcfilt_enb,
adc_dfmt_se,