From 82c4f75f13c9f6fd3bd4af25e4c8f361c9350ca1 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Fri, 22 Apr 2016 10:39:21 -0400 Subject: [PATCH] a10soc- a10gx copy --- .../common/a10soc/a10soc_system_assign.tcl | 240 ++ projects/common/a10soc/a10soc_system_bd.qsys | 2801 +++++++++++++++++ 2 files changed, 3041 insertions(+) create mode 100755 projects/common/a10soc/a10soc_system_assign.tcl create mode 100644 projects/common/a10soc/a10soc_system_bd.qsys diff --git a/projects/common/a10soc/a10soc_system_assign.tcl b/projects/common/a10soc/a10soc_system_assign.tcl new file mode 100755 index 000000000..145c90666 --- /dev/null +++ b/projects/common/a10soc/a10soc_system_assign.tcl @@ -0,0 +1,240 @@ + +# device settings + +set_global_assignment -name FAMILY "Arria 10" +set_global_assignment -name DEVICE 10AX115S3F45E2SGE3 + +# clocks and resets + +set_location_assignment PIN_AR36 -to sys_clk +set_location_assignment PIN_AR37 -to "sys_clk(n)" +set_location_assignment PIN_BD27 -to sys_resetn +set_instance_assignment -name IO_STANDARD LVDS -to sys_clk +set_instance_assignment -name IO_STANDARD "1.8 V" -to sys_resetn + +# ddr3 + +set_location_assignment PIN_F34 -to ddr3_ref_clk +set_location_assignment PIN_F35 -to "ddr3_ref_clk(n)" + +set_instance_assignment -name IO_STANDARD LVDS -to ddr3_ref_clk +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to ddr3_ref_clk -disable + +set_instance_assignment -name IO_STANDARD "1.5 V" -to ddr3_a[14] +set_instance_assignment -name IO_STANDARD "1.5 V" -to ddr3_a[13] +set_instance_assignment -name IO_STANDARD "1.5 V" -to ddr3_a[12] + +set_location_assignment PIN_R30 -to ddr3_clk_p ; ## 1.5 V V1 MEM_CLK_P +set_location_assignment PIN_R31 -to ddr3_clk_n ; ## 1.5 V V2 MEM_CLK_N +set_location_assignment PIN_M32 -to ddr3_a[0] ; ## 1.5 V F1 MEM_ADDR_CMD0 +set_location_assignment PIN_L32 -to ddr3_a[1] ; ## 1.5 V H1 MEM_ADDR_CMD1 +set_location_assignment PIN_N34 -to ddr3_a[2] ; ## 1.5 V F2 MEM_ADDR_CMD2 +set_location_assignment PIN_M35 -to ddr3_a[3] ; ## 1.5 V G2 MEM_ADDR_CMD3 +set_location_assignment PIN_L34 -to ddr3_a[4] ; ## 1.5 V H2 MEM_ADDR_CMD4 +set_location_assignment PIN_K34 -to ddr3_a[5] ; ## 1.5 V J2 MEM_ADDR_CMD5 +set_location_assignment PIN_M33 -to ddr3_a[6] ; ## 1.5 V K2 MEM_ADDR_CMD6 +set_location_assignment PIN_L33 -to ddr3_a[7] ; ## 1.5 V G3 MEM_ADDR_CMD7 +set_location_assignment PIN_J33 -to ddr3_a[8] ; ## 1.5 V J3 MEM_ADDR_CMD8 +set_location_assignment PIN_J32 -to ddr3_a[9] ; ## 1.5 V L3 MEM_ADDR_CMD9 +set_location_assignment PIN_H31 -to ddr3_a[10] ; ## 1.5 V E4 MEM_ADDR_CMD10 +set_location_assignment PIN_J31 -to ddr3_a[11] ; ## 1.5 V F4 MEM_ADDR_CMD11 +set_location_assignment PIN_H34 -to ddr3_a[12] ; ## 1.5 V G4 MEM_ADDR_CMD12 +set_location_assignment PIN_H33 -to ddr3_a[13] ; ## 1.5 V H4 MEM_ADDR_CMD13 +set_location_assignment PIN_G32 -to ddr3_a[14] ; ## 1.5 V J4 MEM_ADDR_CMD14 +set_location_assignment PIN_F33 -to ddr3_ba[0] ; ## 1.5 V M1 MEM_ADDR_CMD16 +set_location_assignment PIN_G35 -to ddr3_ba[1] ; ## 1.5 V M2 MEM_ADDR_CMD17 +set_location_assignment PIN_H35 -to ddr3_ba[2] ; ## 1.5 V N2 MEM_ADDR_CMD18 +set_location_assignment PIN_U33 -to ddr3_cke ; ## 1.5 V P5 MEM_ADDR_CMD20 +set_location_assignment PIN_R34 -to ddr3_cs_n ; ## 1.5 V P1 MEM_ADDR_CMD22 +set_location_assignment PIN_N33 -to ddr3_odt ; ## 1.5 V M4 MEM_ADDR_CMD24 +set_location_assignment PIN_T35 -to ddr3_reset_n ; ## 1.5 V K1 MEM_ADDR_CMD27 +set_location_assignment PIN_T34 -to ddr3_we_n ; ## 1.5 V P2 MEM_ADDR_CMD28 +set_location_assignment PIN_F32 -to ddr3_ras_n ; ## 1.5 V L2 MEM_ADDR_CMD26 +set_location_assignment PIN_G33 -to ddr3_cas_n ; ## 1.5 V L4 MEM_ADDR_CMD19 +set_location_assignment PIN_B26 -to ddr3_dqs_p[0] ; ## 1.5 V A6 MEM_DQSA_P0 +set_location_assignment PIN_C26 -to ddr3_dqs_n[0] ; ## 1.5 V A7 MEM_DQSA_N0 +set_location_assignment PIN_H28 -to ddr3_dqs_p[1] ; ## 1.5 V A2 MEM_DQSA_P1 +set_location_assignment PIN_J27 -to ddr3_dqs_n[1] ; ## 1.5 V A3 MEM_DQSA_N1 +set_location_assignment PIN_C30 -to ddr3_dqs_p[2] ; ## 1.5 V A14 MEM_DQSA_P2 +set_location_assignment PIN_C29 -to ddr3_dqs_n[2] ; ## 1.5 V A15 MEM_DQSA_N2 +set_location_assignment PIN_L30 -to ddr3_dqs_p[3] ; ## 1.5 V F18 MEM_DQSA_P3 +set_location_assignment PIN_L29 -to ddr3_dqs_n[3] ; ## 1.5 V G18 MEM_DQSA_N3 +set_location_assignment PIN_Y32 -to ddr3_dqs_p[4] ; ## 1.5 V H18 MEM_DQSB_P0 +set_location_assignment PIN_AA32 -to ddr3_dqs_n[4] ; ## 1.5 V J18 MEM_DQSB_N0 +set_location_assignment PIN_AJ32 -to ddr3_dqs_p[5] ; ## 1.5 V U18 MEM_DQSB_P1 +set_location_assignment PIN_AJ31 -to ddr3_dqs_n[5] ; ## 1.5 V V18 MEM_DQSB_N1 +set_location_assignment PIN_AA34 -to ddr3_dqs_p[6] ; ## 1.5 V V16 MEM_DQSB_P2 +set_location_assignment PIN_AA33 -to ddr3_dqs_n[6] ; ## 1.5 V V17 MEM_DQSB_N2 +set_location_assignment PIN_AF33 -to ddr3_dqs_p[7] ; ## 1.5 V V8 MEM_DQSB_P3 +set_location_assignment PIN_AF34 -to ddr3_dqs_n[7] ; ## 1.5 V V9 MEM_DQSB_N3 +set_location_assignment PIN_B28 -to ddr3_dq[0] ; ## 1.5 V A4 MEM_DQA0 +set_location_assignment PIN_A28 -to ddr3_dq[1] ; ## 1.5 V B4 MEM_DQA1 +set_location_assignment PIN_A27 -to ddr3_dq[2] ; ## 1.5 V B5 MEM_DQA2 +set_location_assignment PIN_B27 -to ddr3_dq[3] ; ## 1.5 V B6 MEM_DQA3 +set_location_assignment PIN_D27 -to ddr3_dq[4] ; ## 1.5 V A8 MEM_DQA4 +set_location_assignment PIN_E27 -to ddr3_dq[5] ; ## 1.5 V B8 MEM_DQA5 +set_location_assignment PIN_D26 -to ddr3_dq[6] ; ## 1.5 V B9 MEM_DQA6 +set_location_assignment PIN_D28 -to ddr3_dq[7] ; ## 1.5 V A10 MEM_DQA7 +set_location_assignment PIN_G25 -to ddr3_dq[8] ; ## 1.5 V B1 MEM_DQA8 +set_location_assignment PIN_H25 -to ddr3_dq[9] ; ## 1.5 V B2 MEM_DQA9 +set_location_assignment PIN_G26 -to ddr3_dq[10] ; ## 1.5 V C2 MEM_DQA10 +set_location_assignment PIN_H26 -to ddr3_dq[11] ; ## 1.5 V C3 MEM_DQA11 +set_location_assignment PIN_G28 -to ddr3_dq[12] ; ## 1.5 V E3 MEM_DQA12 +set_location_assignment PIN_F27 -to ddr3_dq[13] ; ## 1.5 V D4 MEM_DQA13 +set_location_assignment PIN_K27 -to ddr3_dq[14] ; ## 1.5 V D1 MEM_DQA14 +set_location_assignment PIN_F28 -to ddr3_dq[15] ; ## 1.5 V D2 MEM_DQA15 +set_location_assignment PIN_D31 -to ddr3_dq[16] ; ## 1.5 V A12 MEM_DQA16 +set_location_assignment PIN_E31 -to ddr3_dq[17] ; ## 1.5 V B12 MEM_DQA17 +set_location_assignment PIN_B31 -to ddr3_dq[18] ; ## 1.5 V B13 MEM_DQA18 +set_location_assignment PIN_C31 -to ddr3_dq[19] ; ## 1.5 V B14 MEM_DQA19 +set_location_assignment PIN_A30 -to ddr3_dq[20] ; ## 1.5 V C15 MEM_DQA20 +set_location_assignment PIN_E30 -to ddr3_dq[21] ; ## 1.5 V A16 MEM_DQA21 +set_location_assignment PIN_B30 -to ddr3_dq[22] ; ## 1.5 V B16 MEM_DQA22 +set_location_assignment PIN_D29 -to ddr3_dq[23] ; ## 1.5 V A18 MEM_DQA23 +set_location_assignment PIN_K30 -to ddr3_dq[24] ; ## 1.5 V C16 MEM_DQA24 +set_location_assignment PIN_H30 -to ddr3_dq[25] ; ## 1.5 V D16 MEM_DQA25 +set_location_assignment PIN_G30 -to ddr3_dq[26] ; ## 1.5 V E16 MEM_DQA26 +set_location_assignment PIN_K31 -to ddr3_dq[27] ; ## 1.5 V F16 MEM_DQA27 +set_location_assignment PIN_H29 -to ddr3_dq[28] ; ## 1.5 V D17 MEM_DQA28 +set_location_assignment PIN_K29 -to ddr3_dq[29] ; ## 1.5 V C18 MEM_DQA29 +set_location_assignment PIN_J29 -to ddr3_dq[30] ; ## 1.5 V D18 MEM_DQA30 +set_location_assignment PIN_F29 -to ddr3_dq[31] ; ## 1.5 V E18 MEM_DQA31 +set_location_assignment PIN_AC31 -to ddr3_dq[32] ; ## 1.5 V H16 MEM_DQB0 +set_location_assignment PIN_AB31 -to ddr3_dq[33] ; ## 1.5 V J16 MEM_DQB1 +set_location_assignment PIN_W31 -to ddr3_dq[34] ; ## 1.5 V K16 MEM_DQB2 +set_location_assignment PIN_Y31 -to ddr3_dq[35] ; ## 1.5 V L16 MEM_DQB3 +set_location_assignment PIN_AD31 -to ddr3_dq[36] ; ## 1.5 V H17 MEM_DQB4 +set_location_assignment PIN_AD32 -to ddr3_dq[37] ; ## 1.5 V K17 MEM_DQB5 +set_location_assignment PIN_AD33 -to ddr3_dq[38] ; ## 1.5 V K18 MEM_DQB6 +set_location_assignment PIN_AA30 -to ddr3_dq[39] ; ## 1.5 V L18 MEM_DQB7 +set_location_assignment PIN_AE31 -to ddr3_dq[40] ; ## 1.5 V M17 MEM_DQB8 +set_location_assignment PIN_AE32 -to ddr3_dq[41] ; ## 1.5 V N18 MEM_DQB9 +set_location_assignment PIN_AE30 -to ddr3_dq[42] ; ## 1.5 V P17 MEM_DQB10 +set_location_assignment PIN_AF30 -to ddr3_dq[43] ; ## 1.5 V P18 MEM_DQB11 +set_location_assignment PIN_AG33 -to ddr3_dq[44] ; ## 1.5 V R18 MEM_DQB12 +set_location_assignment PIN_AG32 -to ddr3_dq[45] ; ## 1.5 V T16 MEM_DQB13 +set_location_assignment PIN_AH33 -to ddr3_dq[46] ; ## 1.5 V T17 MEM_DQB14 +set_location_assignment PIN_AH31 -to ddr3_dq[47] ; ## 1.5 V T18 MEM_DQB15 +set_location_assignment PIN_U31 -to ddr3_dq[48] ; ## 1.5 V U15 MEM_DQB16 +set_location_assignment PIN_W33 -to ddr3_dq[49] ; ## 1.5 V T14 MEM_DQB17 +set_location_assignment PIN_W32 -to ddr3_dq[50] ; ## 1.5 V U14 MEM_DQB18 +set_location_assignment PIN_V31 -to ddr3_dq[51] ; ## 1.5 V V14 MEM_DQB19 +set_location_assignment PIN_Y34 -to ddr3_dq[52] ; ## 1.5 V T13 MEM_DQB20 +set_location_assignment PIN_W35 -to ddr3_dq[53] ; ## 1.5 V T12 MEM_DQB21 +set_location_assignment PIN_W34 -to ddr3_dq[54] ; ## 1.5 V U12 MEM_DQB22 +set_location_assignment PIN_V34 -to ddr3_dq[55] ; ## 1.5 V V12 MEM_DQB23 +set_location_assignment PIN_AH35 -to ddr3_dq[56] ; ## 1.5 V T10 MEM_DQB24 +set_location_assignment PIN_AJ34 -to ddr3_dq[57] ; ## 1.5 V U10 MEM_DQB25 +set_location_assignment PIN_AJ33 -to ddr3_dq[58] ; ## 1.5 V V10 MEM_DQB26 +set_location_assignment PIN_AH34 -to ddr3_dq[59] ; ## 1.5 V T9 MEM_DQB27 +set_location_assignment PIN_AD35 -to ddr3_dq[60] ; ## 1.5 V T8 MEM_DQB28 +set_location_assignment PIN_AE34 -to ddr3_dq[61] ; ## 1.5 V U8 MEM_DQB29 +set_location_assignment PIN_AC33 -to ddr3_dq[62] ; ## 1.5 V U7 MEM_DQB30 +set_location_assignment PIN_AD34 -to ddr3_dq[63] ; ## 1.5 V V6 MEM_DQB31 +set_location_assignment PIN_E26 -to ddr3_dm[0] ; ## 1.5 V B10 MEM_DMA0 +set_location_assignment PIN_G27 -to ddr3_dm[1] ; ## 1.5 V C4 MEM_DMA1 +set_location_assignment PIN_A29 -to ddr3_dm[2] ; ## 1.5 V B17 MEM_DMA2 +set_location_assignment PIN_F30 -to ddr3_dm[3] ; ## 1.5 V F17 MEM_DMA3 +set_location_assignment PIN_AB32 -to ddr3_dm[4] ; ## 1.5 V M16 MEM_DMB0 +set_location_assignment PIN_AG31 -to ddr3_dm[5] ; ## 1.5 V U16 MEM_DMB1 +set_location_assignment PIN_Y35 -to ddr3_dm[6] ; ## 1.5 V U11 MEM_DMB2 +set_location_assignment PIN_AC34 -to ddr3_dm[7] ; ## 1.5 V U6 MEM_DMB3 +set_location_assignment PIN_J34 -to ddr3_rzq ; ## RZQ + +# ethernet interface + +set_location_assignment PIN_BD24 -to eth_ref_clk +set_location_assignment PIN_BC24 -to "eth_ref_clk(n)" +set_location_assignment PIN_AV24 -to eth_rxd +set_location_assignment PIN_AW24 -to "eth_rxd(n)" +set_location_assignment PIN_BC23 -to eth_txd +set_location_assignment PIN_BD23 -to "eth_txd(n)" + +set_instance_assignment -name IO_STANDARD LVDS -to eth_ref_clk +set_instance_assignment -name IO_STANDARD LVDS -to eth_rxd +set_instance_assignment -name IO_STANDARD LVDS -to eth_txd + +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to eth_ref_clk -disable +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to eth_rxd -disable + +set_location_assignment PIN_AW23 -to eth_resetn +set_location_assignment PIN_AF13 -to eth_mdc +set_location_assignment PIN_AL18 -to eth_mdio +set_location_assignment PIN_AG13 -to eth_intn + +set_instance_assignment -name IO_STANDARD "1.8 V" -to eth_resetn +set_instance_assignment -name IO_STANDARD "1.8 V" -to eth_mdc +set_instance_assignment -name IO_STANDARD "1.8 V" -to eth_mdio +set_instance_assignment -name IO_STANDARD "1.8 V" -to eth_intn + +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to eth_ref_clk + +# leds + +set_location_assignment PIN_L28 -to gpio_bd_o[0] ; ## led-g0-d10 +set_location_assignment PIN_K26 -to gpio_bd_o[1] ; ## led-g1-d9 +set_location_assignment PIN_K25 -to gpio_bd_o[2] ; ## led-g2-d8 +set_location_assignment PIN_L25 -to gpio_bd_o[3] ; ## led-g3-d7 +set_location_assignment PIN_J24 -to gpio_bd_o[4] ; ## led-g4-d6 +set_location_assignment PIN_A19 -to gpio_bd_o[5] ; ## led-g5-d5 +set_location_assignment PIN_C18 -to gpio_bd_o[6] ; ## led-g6-d4 +set_location_assignment PIN_D18 -to gpio_bd_o[7] ; ## led-g7-d3 +set_location_assignment PIN_L27 -to gpio_bd_o[8] ; ## led-r0-d10 +set_location_assignment PIN_J26 -to gpio_bd_o[9] ; ## led-r1-d9 +set_location_assignment PIN_K24 -to gpio_bd_o[10] ; ## led-r2-d8 +set_location_assignment PIN_L23 -to gpio_bd_o[11] ; ## led-r3-d7 +set_location_assignment PIN_B20 -to gpio_bd_o[12] ; ## led-r4-d6 +set_location_assignment PIN_C19 -to gpio_bd_o[13] ; ## led-r5-d5 +set_location_assignment PIN_D19 -to gpio_bd_o[14] ; ## led-r6-d4 +set_location_assignment PIN_M23 -to gpio_bd_o[15] ; ## led-r7-d3 +set_location_assignment PIN_A24 -to gpio_bd_i[0] ; ## dipsw0 +set_location_assignment PIN_B23 -to gpio_bd_i[1] ; ## dipsw1 +set_location_assignment PIN_A23 -to gpio_bd_i[2] ; ## dipsw2 +set_location_assignment PIN_B22 -to gpio_bd_i[3] ; ## dipsw3 +set_location_assignment PIN_A22 -to gpio_bd_i[4] ; ## dipsw4 +set_location_assignment PIN_B21 -to gpio_bd_i[5] ; ## dipsw5 +set_location_assignment PIN_C21 -to gpio_bd_i[6] ; ## dipsw6 +set_location_assignment PIN_A20 -to gpio_bd_i[7] ; ## dipsw7 +set_location_assignment PIN_T12 -to gpio_bd_i[8] ; ## pb0-s3 +set_location_assignment PIN_U12 -to gpio_bd_i[9] ; ## pb1-s2 +set_location_assignment PIN_U11 -to gpio_bd_i[10] ; ## pb2-s1 + +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[11] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[12] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[13] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[14] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[15] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[10] + +# globals + +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO +set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON +set_global_assignment -name TIMEQUEST_REPORT_SCRIPT $ad_hdl_dir/projects/scripts/adi_tquest.tcl +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF + + diff --git a/projects/common/a10soc/a10soc_system_bd.qsys b/projects/common/a10soc/a10soc_system_bd.qsys new file mode 100644 index 000000000..7bdd08068 --- /dev/null +++ b/projects/common/a10soc/a10soc_system_bd.qsys @@ -0,0 +1,2801 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + sys_cpu.jtag_debug_module + + + + + + + + + + + + + ]]> + + + + + + + + + + + + + + + + + + + + + + ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 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ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $${FILENAME}_sys_tlb_mem + + + + + ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0 + + + + + + + + + + + + + + + + + + + + + + + + + + NO_INTERACTIVE_WINDOWS + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +